llama.cpp/docs/ops/CUDA.csv

1	backend_name	op_name	op_params	test_mode	supported	error_message	backend_reg_name
2	CUDA0	ABS	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
3	CUDA0	ABS	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
4	CUDA0	SGN	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
5	CUDA0	SGN	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
6	CUDA0	NEG	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
7	CUDA0	NEG	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
8	CUDA0	STEP	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
9	CUDA0	STEP	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
10	CUDA0	TANH	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
11	CUDA0	TANH	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
12	CUDA0	ELU	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
13	CUDA0	ELU	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
14	CUDA0	RELU	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
15	CUDA0	RELU	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
16	CUDA0	SIGMOID	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
17	CUDA0	SIGMOID	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
18	CUDA0	GELU	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
19	CUDA0	GELU	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
20	CUDA0	GELU_QUICK	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
21	CUDA0	GELU_QUICK	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
22	CUDA0	SILU	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
23	CUDA0	SILU	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
24	CUDA0	HARDSWISH	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
25	CUDA0	HARDSWISH	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
26	CUDA0	HARDSIGMOID	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
27	CUDA0	HARDSIGMOID	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
28	CUDA0	EXP	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
29	CUDA0	EXP	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
30	CUDA0	GELU_ERF	type=f16,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
31	CUDA0	GELU_ERF	type=f16,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
32	CUDA0	ABS	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
33	CUDA0	ABS	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
34	CUDA0	SGN	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
35	CUDA0	SGN	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
36	CUDA0	NEG	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
37	CUDA0	NEG	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
38	CUDA0	STEP	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
39	CUDA0	STEP	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
40	CUDA0	TANH	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
41	CUDA0	TANH	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
42	CUDA0	ELU	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
43	CUDA0	ELU	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
44	CUDA0	RELU	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
45	CUDA0	RELU	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
46	CUDA0	SIGMOID	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
47	CUDA0	SIGMOID	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
48	CUDA0	GELU	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
49	CUDA0	GELU	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
50	CUDA0	GELU_QUICK	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
51	CUDA0	GELU_QUICK	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
52	CUDA0	SILU	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
53	CUDA0	SILU	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
54	CUDA0	HARDSWISH	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
55	CUDA0	HARDSWISH	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
56	CUDA0	HARDSIGMOID	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
57	CUDA0	HARDSIGMOID	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
58	CUDA0	EXP	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
59	CUDA0	EXP	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
60	CUDA0	GELU_ERF	type=f16,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
61	CUDA0	GELU_ERF	type=f16,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
62	CUDA0	ABS	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
63	CUDA0	ABS	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
64	CUDA0	SGN	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
65	CUDA0	SGN	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
66	CUDA0	NEG	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
67	CUDA0	NEG	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
68	CUDA0	STEP	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
69	CUDA0	STEP	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
70	CUDA0	TANH	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
71	CUDA0	TANH	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
72	CUDA0	ELU	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
73	CUDA0	ELU	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
74	CUDA0	RELU	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
75	CUDA0	RELU	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
76	CUDA0	SIGMOID	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
77	CUDA0	SIGMOID	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
78	CUDA0	GELU	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
79	CUDA0	GELU	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
80	CUDA0	GELU_QUICK	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
81	CUDA0	GELU_QUICK	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
82	CUDA0	SILU	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
83	CUDA0	SILU	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
84	CUDA0	HARDSWISH	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
85	CUDA0	HARDSWISH	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
86	CUDA0	HARDSIGMOID	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
87	CUDA0	HARDSIGMOID	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
88	CUDA0	EXP	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
89	CUDA0	EXP	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
90	CUDA0	GELU_ERF	type=f32,ne_a=[128,2,2,2],v=0	support	1	yes	CUDA
91	CUDA0	GELU_ERF	type=f32,ne_a=[5,7,11,13],v=0	support	1	yes	CUDA
92	CUDA0	ABS	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
93	CUDA0	ABS	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
94	CUDA0	SGN	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
95	CUDA0	SGN	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
96	CUDA0	NEG	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
97	CUDA0	NEG	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
98	CUDA0	STEP	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
99	CUDA0	STEP	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
100	CUDA0	TANH	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
101	CUDA0	TANH	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
102	CUDA0	ELU	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
103	CUDA0	ELU	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
104	CUDA0	RELU	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
105	CUDA0	RELU	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
106	CUDA0	SIGMOID	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
107	CUDA0	SIGMOID	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
108	CUDA0	GELU	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
109	CUDA0	GELU	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
110	CUDA0	GELU_QUICK	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
111	CUDA0	GELU_QUICK	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
112	CUDA0	SILU	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
113	CUDA0	SILU	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
114	CUDA0	HARDSWISH	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
115	CUDA0	HARDSWISH	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
116	CUDA0	HARDSIGMOID	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
117	CUDA0	HARDSIGMOID	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
118	CUDA0	EXP	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
119	CUDA0	EXP	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
120	CUDA0	GELU_ERF	type=f32,ne_a=[128,2,2,2],v=1	support	0	no	CUDA
121	CUDA0	GELU_ERF	type=f32,ne_a=[5,7,11,13],v=1	support	0	no	CUDA
122	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
123	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
124	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
125	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
126	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
127	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
128	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
129	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
130	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
131	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
132	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
133	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
134	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
135	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
136	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
137	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
138	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
139	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
140	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
141	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
142	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
143	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
144	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
145	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
146	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
147	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
148	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
149	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
150	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
151	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
152	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
153	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
154	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
155	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
156	CUDA0	REGLU	type=f16,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
157	CUDA0	REGLU	type=f16,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
158	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
159	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
160	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
161	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
162	CUDA0	GEGLU	type=f16,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
163	CUDA0	GEGLU	type=f16,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
164	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
165	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
166	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
167	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
168	CUDA0	SWIGLU	type=f16,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
169	CUDA0	SWIGLU	type=f16,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
170	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
171	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
172	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
173	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
174	CUDA0	GEGLU_ERF	type=f16,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
175	CUDA0	GEGLU_ERF	type=f16,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
176	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
177	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
178	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
179	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
180	CUDA0	GEGLU_QUICK	type=f16,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
181	CUDA0	GEGLU_QUICK	type=f16,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
182	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
183	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
184	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
185	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
186	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
187	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
188	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
189	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
190	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
191	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
192	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
193	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
194	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
195	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
196	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
197	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
198	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
199	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
200	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
201	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
202	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
203	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
204	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
205	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
206	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=0,swapped=0	support	1	yes	CUDA
207	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=0,swapped=0	support	1	yes	CUDA
208	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=0,swapped=1	support	1	yes	CUDA
209	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=0,swapped=1	support	1	yes	CUDA
210	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=0,split	support	1	yes	CUDA
211	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=0,split	support	1	yes	CUDA
212	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
213	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
214	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
215	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
216	CUDA0	REGLU	type=f32,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
217	CUDA0	REGLU	type=f32,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
218	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
219	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
220	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
221	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
222	CUDA0	GEGLU	type=f32,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
223	CUDA0	GEGLU	type=f32,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
224	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
225	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
226	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
227	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
228	CUDA0	SWIGLU	type=f32,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
229	CUDA0	SWIGLU	type=f32,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
230	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
231	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
232	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
233	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
234	CUDA0	GEGLU_ERF	type=f32,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
235	CUDA0	GEGLU_ERF	type=f32,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
236	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=1,swapped=0	support	1	yes	CUDA
237	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=1,swapped=0	support	1	yes	CUDA
238	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=1,swapped=1	support	1	yes	CUDA
239	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=1,swapped=1	support	1	yes	CUDA
240	CUDA0	GEGLU_QUICK	type=f32,ne_a=[128,2,2,2],v=1,split	support	1	yes	CUDA
241	CUDA0	GEGLU_QUICK	type=f32,ne_a=[5,7,11,13],v=1,split	support	1	yes	CUDA
242	CUDA0	GET_ROWS	type=f32,n=1,m=8,r=2,b=1,v=0	support	1	yes	CUDA
243	CUDA0	GET_ROWS	type=f32,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
244	CUDA0	GET_ROWS	type=f32,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
245	CUDA0	GET_ROWS	type=f32,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
246	CUDA0	GET_ROWS	type=f32,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
247	CUDA0	GET_ROWS	type=f16,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
248	CUDA0	GET_ROWS	type=f16,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
249	CUDA0	GET_ROWS	type=f16,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
250	CUDA0	GET_ROWS	type=f16,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
251	CUDA0	GET_ROWS	type=bf16,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
252	CUDA0	GET_ROWS	type=bf16,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
253	CUDA0	GET_ROWS	type=bf16,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
254	CUDA0	GET_ROWS	type=bf16,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
255	CUDA0	GET_ROWS	type=q4_0,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
256	CUDA0	GET_ROWS	type=q4_0,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
257	CUDA0	GET_ROWS	type=q4_0,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
258	CUDA0	GET_ROWS	type=q4_0,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
259	CUDA0	GET_ROWS	type=q4_1,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
260	CUDA0	GET_ROWS	type=q4_1,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
261	CUDA0	GET_ROWS	type=q4_1,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
262	CUDA0	GET_ROWS	type=q4_1,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
263	CUDA0	GET_ROWS	type=q5_0,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
264	CUDA0	GET_ROWS	type=q5_0,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
265	CUDA0	GET_ROWS	type=q5_0,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
266	CUDA0	GET_ROWS	type=q5_0,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
267	CUDA0	GET_ROWS	type=q5_1,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
268	CUDA0	GET_ROWS	type=q5_1,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
269	CUDA0	GET_ROWS	type=q5_1,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
270	CUDA0	GET_ROWS	type=q5_1,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
271	CUDA0	GET_ROWS	type=q8_0,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
272	CUDA0	GET_ROWS	type=q8_0,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
273	CUDA0	GET_ROWS	type=q8_0,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
274	CUDA0	GET_ROWS	type=q8_0,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
275	CUDA0	GET_ROWS	type=q2_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
276	CUDA0	GET_ROWS	type=q2_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
277	CUDA0	GET_ROWS	type=q2_K,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
278	CUDA0	GET_ROWS	type=q2_K,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
279	CUDA0	GET_ROWS	type=q3_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
280	CUDA0	GET_ROWS	type=q3_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
281	CUDA0	GET_ROWS	type=q3_K,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
282	CUDA0	GET_ROWS	type=q3_K,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
283	CUDA0	GET_ROWS	type=q4_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
284	CUDA0	GET_ROWS	type=q4_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
285	CUDA0	GET_ROWS	type=q4_K,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
286	CUDA0	GET_ROWS	type=q4_K,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
287	CUDA0	GET_ROWS	type=q5_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
288	CUDA0	GET_ROWS	type=q5_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
289	CUDA0	GET_ROWS	type=q5_K,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
290	CUDA0	GET_ROWS	type=q5_K,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
291	CUDA0	GET_ROWS	type=q6_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
292	CUDA0	GET_ROWS	type=q6_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
293	CUDA0	GET_ROWS	type=q6_K,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
294	CUDA0	GET_ROWS	type=q6_K,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
295	CUDA0	GET_ROWS	type=iq2_xxs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
296	CUDA0	GET_ROWS	type=iq2_xxs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
297	CUDA0	GET_ROWS	type=iq2_xxs,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
298	CUDA0	GET_ROWS	type=iq2_xxs,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
299	CUDA0	GET_ROWS	type=iq2_xs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
300	CUDA0	GET_ROWS	type=iq2_xs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
301	CUDA0	GET_ROWS	type=iq2_xs,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
302	CUDA0	GET_ROWS	type=iq2_xs,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
303	CUDA0	GET_ROWS	type=iq2_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
304	CUDA0	GET_ROWS	type=iq2_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
305	CUDA0	GET_ROWS	type=iq2_s,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
306	CUDA0	GET_ROWS	type=iq2_s,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
307	CUDA0	GET_ROWS	type=iq3_xxs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
308	CUDA0	GET_ROWS	type=iq3_xxs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
309	CUDA0	GET_ROWS	type=iq3_xxs,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
310	CUDA0	GET_ROWS	type=iq3_xxs,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
311	CUDA0	GET_ROWS	type=iq1_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
312	CUDA0	GET_ROWS	type=iq1_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
313	CUDA0	GET_ROWS	type=iq1_s,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
314	CUDA0	GET_ROWS	type=iq1_s,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
315	CUDA0	GET_ROWS	type=iq1_m,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
316	CUDA0	GET_ROWS	type=iq1_m,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
317	CUDA0	GET_ROWS	type=iq1_m,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
318	CUDA0	GET_ROWS	type=iq1_m,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
319	CUDA0	GET_ROWS	type=iq4_nl,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
320	CUDA0	GET_ROWS	type=iq4_nl,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
321	CUDA0	GET_ROWS	type=iq4_nl,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
322	CUDA0	GET_ROWS	type=iq4_nl,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
323	CUDA0	GET_ROWS	type=iq3_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
324	CUDA0	GET_ROWS	type=iq3_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
325	CUDA0	GET_ROWS	type=iq3_s,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
326	CUDA0	GET_ROWS	type=iq3_s,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
327	CUDA0	GET_ROWS	type=iq4_xs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
328	CUDA0	GET_ROWS	type=iq4_xs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
329	CUDA0	GET_ROWS	type=iq4_xs,n=256,m=5,r=4,b=7,v=0	support	0	no	CUDA
330	CUDA0	GET_ROWS	type=iq4_xs,n=256,m=5,r=4,b=7,v=1	support	0	no	CUDA
331	CUDA0	GET_ROWS	type=i32,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
332	CUDA0	GET_ROWS	type=i32,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
333	CUDA0	GET_ROWS	type=i32,n=256,m=5,r=4,b=7,v=0	support	1	yes	CUDA
334	CUDA0	GET_ROWS	type=i32,n=256,m=5,r=4,b=7,v=1	support	1	yes	CUDA
335	CUDA0	GET_ROWS_BACK	type=f32,n=1,m=8,r=2,b=1,v=0	support	1	yes	CUDA
336	CUDA0	GET_ROWS_BACK	type=f32,n=256,m=5,r=4,b=1,v=0	support	1	yes	CUDA
337	CUDA0	GET_ROWS_BACK	type=f32,n=256,m=5,r=4,b=1,v=1	support	1	yes	CUDA
338	CUDA0	GET_ROWS_BACK	type=f16,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
339	CUDA0	GET_ROWS_BACK	type=f16,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
340	CUDA0	GET_ROWS_BACK	type=bf16,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
341	CUDA0	GET_ROWS_BACK	type=bf16,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
342	CUDA0	GET_ROWS_BACK	type=q4_0,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
343	CUDA0	GET_ROWS_BACK	type=q4_0,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
344	CUDA0	GET_ROWS_BACK	type=q4_1,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
345	CUDA0	GET_ROWS_BACK	type=q4_1,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
346	CUDA0	GET_ROWS_BACK	type=q5_0,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
347	CUDA0	GET_ROWS_BACK	type=q5_0,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
348	CUDA0	GET_ROWS_BACK	type=q5_1,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
349	CUDA0	GET_ROWS_BACK	type=q5_1,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
350	CUDA0	GET_ROWS_BACK	type=q8_0,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
351	CUDA0	GET_ROWS_BACK	type=q8_0,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
352	CUDA0	GET_ROWS_BACK	type=q2_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
353	CUDA0	GET_ROWS_BACK	type=q2_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
354	CUDA0	GET_ROWS_BACK	type=q3_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
355	CUDA0	GET_ROWS_BACK	type=q3_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
356	CUDA0	GET_ROWS_BACK	type=q4_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
357	CUDA0	GET_ROWS_BACK	type=q4_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
358	CUDA0	GET_ROWS_BACK	type=q5_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
359	CUDA0	GET_ROWS_BACK	type=q5_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
360	CUDA0	GET_ROWS_BACK	type=q6_K,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
361	CUDA0	GET_ROWS_BACK	type=q6_K,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
362	CUDA0	GET_ROWS_BACK	type=iq2_xxs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
363	CUDA0	GET_ROWS_BACK	type=iq2_xxs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
364	CUDA0	GET_ROWS_BACK	type=iq2_xs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
365	CUDA0	GET_ROWS_BACK	type=iq2_xs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
366	CUDA0	GET_ROWS_BACK	type=iq2_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
367	CUDA0	GET_ROWS_BACK	type=iq2_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
368	CUDA0	GET_ROWS_BACK	type=iq3_xxs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
369	CUDA0	GET_ROWS_BACK	type=iq3_xxs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
370	CUDA0	GET_ROWS_BACK	type=iq1_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
371	CUDA0	GET_ROWS_BACK	type=iq1_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
372	CUDA0	GET_ROWS_BACK	type=iq1_m,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
373	CUDA0	GET_ROWS_BACK	type=iq1_m,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
374	CUDA0	GET_ROWS_BACK	type=iq4_nl,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
375	CUDA0	GET_ROWS_BACK	type=iq4_nl,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
376	CUDA0	GET_ROWS_BACK	type=iq3_s,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
377	CUDA0	GET_ROWS_BACK	type=iq3_s,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
378	CUDA0	GET_ROWS_BACK	type=iq4_xs,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
379	CUDA0	GET_ROWS_BACK	type=iq4_xs,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
380	CUDA0	GET_ROWS_BACK	type=i32,n=256,m=5,r=4,b=1,v=0	support	0	no	CUDA
381	CUDA0	GET_ROWS_BACK	type=i32,n=256,m=5,r=4,b=1,v=1	support	0	no	CUDA
382	CUDA0	SET_ROWS	type=f32,ne=[1,8,1,3],nr23=[1,1],r=2,v=0	support	1	yes	CUDA
383	CUDA0	SET_ROWS	type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
384	CUDA0	SET_ROWS	type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
385	CUDA0	SET_ROWS	type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
386	CUDA0	SET_ROWS	type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
387	CUDA0	SET_ROWS	type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
388	CUDA0	SET_ROWS	type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
389	CUDA0	SET_ROWS	type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
390	CUDA0	SET_ROWS	type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
391	CUDA0	SET_ROWS	type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
392	CUDA0	SET_ROWS	type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
393	CUDA0	SET_ROWS	type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
394	CUDA0	SET_ROWS	type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
395	CUDA0	SET_ROWS	type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
396	CUDA0	SET_ROWS	type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
397	CUDA0	SET_ROWS	type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
398	CUDA0	SET_ROWS	type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
399	CUDA0	SET_ROWS	type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
400	CUDA0	SET_ROWS	type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
401	CUDA0	SET_ROWS	type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
402	CUDA0	SET_ROWS	type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
403	CUDA0	SET_ROWS	type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
404	CUDA0	SET_ROWS	type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
405	CUDA0	SET_ROWS	type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
406	CUDA0	SET_ROWS	type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
407	CUDA0	SET_ROWS	type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
408	CUDA0	SET_ROWS	type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
409	CUDA0	SET_ROWS	type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
410	CUDA0	SET_ROWS	type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
411	CUDA0	SET_ROWS	type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
412	CUDA0	SET_ROWS	type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
413	CUDA0	SET_ROWS	type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
414	CUDA0	SET_ROWS	type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
415	CUDA0	SET_ROWS	type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
416	CUDA0	SET_ROWS	type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
417	CUDA0	SET_ROWS	type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
418	CUDA0	SET_ROWS	type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
419	CUDA0	SET_ROWS	type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
420	CUDA0	SET_ROWS	type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
421	CUDA0	SET_ROWS	type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
422	CUDA0	SET_ROWS	type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
423	CUDA0	SET_ROWS	type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
424	CUDA0	SET_ROWS	type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
425	CUDA0	SET_ROWS	type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
426	CUDA0	SET_ROWS	type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
427	CUDA0	SET_ROWS	type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
428	CUDA0	SET_ROWS	type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
429	CUDA0	SET_ROWS	type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
430	CUDA0	SET_ROWS	type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
431	CUDA0	SET_ROWS	type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
432	CUDA0	SET_ROWS	type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
433	CUDA0	SET_ROWS	type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
434	CUDA0	SET_ROWS	type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
435	CUDA0	SET_ROWS	type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
436	CUDA0	SET_ROWS	type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
437	CUDA0	SET_ROWS	type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0	support	1	yes	CUDA
438	CUDA0	SET_ROWS	type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
439	CUDA0	SET_ROWS	type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
440	CUDA0	SET_ROWS	type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
441	CUDA0	SET_ROWS	type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
442	CUDA0	SET_ROWS	type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1	support	1	yes	CUDA
443	CUDA0	SET_ROWS	type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
444	CUDA0	SET_ROWS	type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
445	CUDA0	SET_ROWS	type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
446	CUDA0	SET_ROWS	type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
447	CUDA0	SET_ROWS	type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
448	CUDA0	SET_ROWS	type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
449	CUDA0	SET_ROWS	type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
450	CUDA0	SET_ROWS	type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
451	CUDA0	SET_ROWS	type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
452	CUDA0	SET_ROWS	type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
453	CUDA0	SET_ROWS	type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
454	CUDA0	SET_ROWS	type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
455	CUDA0	SET_ROWS	type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
456	CUDA0	SET_ROWS	type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
457	CUDA0	SET_ROWS	type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
458	CUDA0	SET_ROWS	type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
459	CUDA0	SET_ROWS	type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
460	CUDA0	SET_ROWS	type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
461	CUDA0	SET_ROWS	type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
462	CUDA0	SET_ROWS	type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
463	CUDA0	SET_ROWS	type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
464	CUDA0	SET_ROWS	type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
465	CUDA0	SET_ROWS	type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
466	CUDA0	SET_ROWS	type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
467	CUDA0	SET_ROWS	type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
468	CUDA0	SET_ROWS	type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
469	CUDA0	SET_ROWS	type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
470	CUDA0	SET_ROWS	type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
471	CUDA0	SET_ROWS	type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
472	CUDA0	SET_ROWS	type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
473	CUDA0	SET_ROWS	type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
474	CUDA0	SET_ROWS	type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
475	CUDA0	SET_ROWS	type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
476	CUDA0	SET_ROWS	type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
477	CUDA0	SET_ROWS	type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
478	CUDA0	SET_ROWS	type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
479	CUDA0	SET_ROWS	type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
480	CUDA0	SET_ROWS	type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
481	CUDA0	SET_ROWS	type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
482	CUDA0	SET_ROWS	type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
483	CUDA0	SET_ROWS	type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
484	CUDA0	SET_ROWS	type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
485	CUDA0	SET_ROWS	type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
486	CUDA0	SET_ROWS	type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
487	CUDA0	SET_ROWS	type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
488	CUDA0	SET_ROWS	type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
489	CUDA0	SET_ROWS	type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
490	CUDA0	SET_ROWS	type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
491	CUDA0	SET_ROWS	type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
492	CUDA0	SET_ROWS	type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
493	CUDA0	SET_ROWS	type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
494	CUDA0	SET_ROWS	type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
495	CUDA0	SET_ROWS	type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
496	CUDA0	SET_ROWS	type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
497	CUDA0	SET_ROWS	type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
498	CUDA0	SET_ROWS	type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
499	CUDA0	SET_ROWS	type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
500	CUDA0	SET_ROWS	type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
501	CUDA0	SET_ROWS	type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
502	CUDA0	SET_ROWS	type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
503	CUDA0	SET_ROWS	type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
504	CUDA0	SET_ROWS	type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
505	CUDA0	SET_ROWS	type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
506	CUDA0	SET_ROWS	type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
507	CUDA0	SET_ROWS	type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
508	CUDA0	SET_ROWS	type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
509	CUDA0	SET_ROWS	type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
510	CUDA0	SET_ROWS	type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
511	CUDA0	SET_ROWS	type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
512	CUDA0	SET_ROWS	type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
513	CUDA0	SET_ROWS	type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
514	CUDA0	SET_ROWS	type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
515	CUDA0	SET_ROWS	type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
516	CUDA0	SET_ROWS	type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
517	CUDA0	SET_ROWS	type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
518	CUDA0	SET_ROWS	type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
519	CUDA0	SET_ROWS	type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
520	CUDA0	SET_ROWS	type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
521	CUDA0	SET_ROWS	type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
522	CUDA0	SET_ROWS	type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
523	CUDA0	SET_ROWS	type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
524	CUDA0	SET_ROWS	type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
525	CUDA0	SET_ROWS	type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
526	CUDA0	SET_ROWS	type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
527	CUDA0	SET_ROWS	type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
528	CUDA0	SET_ROWS	type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
529	CUDA0	SET_ROWS	type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
530	CUDA0	SET_ROWS	type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
531	CUDA0	SET_ROWS	type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
532	CUDA0	SET_ROWS	type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
533	CUDA0	SET_ROWS	type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
534	CUDA0	SET_ROWS	type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
535	CUDA0	SET_ROWS	type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
536	CUDA0	SET_ROWS	type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
537	CUDA0	SET_ROWS	type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
538	CUDA0	SET_ROWS	type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
539	CUDA0	SET_ROWS	type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
540	CUDA0	SET_ROWS	type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
541	CUDA0	SET_ROWS	type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
542	CUDA0	SET_ROWS	type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
543	CUDA0	SET_ROWS	type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
544	CUDA0	SET_ROWS	type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
545	CUDA0	SET_ROWS	type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
546	CUDA0	SET_ROWS	type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
547	CUDA0	SET_ROWS	type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
548	CUDA0	SET_ROWS	type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
549	CUDA0	SET_ROWS	type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
550	CUDA0	SET_ROWS	type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
551	CUDA0	SET_ROWS	type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
552	CUDA0	SET_ROWS	type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
553	CUDA0	SET_ROWS	type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
554	CUDA0	SET_ROWS	type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
555	CUDA0	SET_ROWS	type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
556	CUDA0	SET_ROWS	type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
557	CUDA0	SET_ROWS	type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
558	CUDA0	SET_ROWS	type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
559	CUDA0	SET_ROWS	type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
560	CUDA0	SET_ROWS	type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
561	CUDA0	SET_ROWS	type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
562	CUDA0	SET_ROWS	type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
563	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
564	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
565	CUDA0	SET_ROWS	type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
566	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
567	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
568	CUDA0	SET_ROWS	type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
569	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
570	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
571	CUDA0	SET_ROWS	type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
572	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
573	CUDA0	SET_ROWS	type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
574	CUDA0	SET_ROWS	type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
575	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
576	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
577	CUDA0	SET_ROWS	type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
578	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
579	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
580	CUDA0	SET_ROWS	type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
581	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
582	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
583	CUDA0	SET_ROWS	type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
584	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
585	CUDA0	SET_ROWS	type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
586	CUDA0	SET_ROWS	type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
587	CUDA0	SET_ROWS	type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
588	CUDA0	SET_ROWS	type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
589	CUDA0	SET_ROWS	type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
590	CUDA0	SET_ROWS	type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
591	CUDA0	SET_ROWS	type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
592	CUDA0	SET_ROWS	type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
593	CUDA0	SET_ROWS	type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
594	CUDA0	SET_ROWS	type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
595	CUDA0	SET_ROWS	type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
596	CUDA0	SET_ROWS	type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
597	CUDA0	SET_ROWS	type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
598	CUDA0	SET_ROWS	type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
599	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
600	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
601	CUDA0	SET_ROWS	type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
602	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
603	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
604	CUDA0	SET_ROWS	type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
605	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
606	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
607	CUDA0	SET_ROWS	type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
608	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
609	CUDA0	SET_ROWS	type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
610	CUDA0	SET_ROWS	type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
611	CUDA0	SET_ROWS	type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
612	CUDA0	SET_ROWS	type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
613	CUDA0	SET_ROWS	type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
614	CUDA0	SET_ROWS	type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
615	CUDA0	SET_ROWS	type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
616	CUDA0	SET_ROWS	type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
617	CUDA0	SET_ROWS	type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
618	CUDA0	SET_ROWS	type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
619	CUDA0	SET_ROWS	type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
620	CUDA0	SET_ROWS	type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
621	CUDA0	SET_ROWS	type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
622	CUDA0	SET_ROWS	type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
623	CUDA0	SET_ROWS	type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
624	CUDA0	SET_ROWS	type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
625	CUDA0	SET_ROWS	type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
626	CUDA0	SET_ROWS	type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
627	CUDA0	SET_ROWS	type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
628	CUDA0	SET_ROWS	type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
629	CUDA0	SET_ROWS	type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
630	CUDA0	SET_ROWS	type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
631	CUDA0	SET_ROWS	type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
632	CUDA0	SET_ROWS	type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
633	CUDA0	SET_ROWS	type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
634	CUDA0	SET_ROWS	type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
635	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
636	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
637	CUDA0	SET_ROWS	type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
638	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
639	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
640	CUDA0	SET_ROWS	type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
641	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	1	yes	CUDA
642	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	1	yes	CUDA
643	CUDA0	SET_ROWS	type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=0	support	1	yes	CUDA
644	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	1	yes	CUDA
645	CUDA0	SET_ROWS	type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	1	yes	CUDA
646	CUDA0	SET_ROWS	type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=1	support	1	yes	CUDA
647	CUDA0	SET_ROWS	type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
648	CUDA0	SET_ROWS	type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
649	CUDA0	SET_ROWS	type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
650	CUDA0	SET_ROWS	type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
651	CUDA0	SET_ROWS	type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
652	CUDA0	SET_ROWS	type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
653	CUDA0	SET_ROWS	type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
654	CUDA0	SET_ROWS	type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
655	CUDA0	SET_ROWS	type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
656	CUDA0	SET_ROWS	type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
657	CUDA0	SET_ROWS	type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
658	CUDA0	SET_ROWS	type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
659	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
660	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0	support	0	no	CUDA
661	CUDA0	SET_ROWS	type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
662	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
663	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1	support	0	no	CUDA
664	CUDA0	SET_ROWS	type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
665	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0	support	0	no	CUDA
666	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0	support	0	no	CUDA
667	CUDA0	SET_ROWS	type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0	support	0	no	CUDA
668	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1	support	0	no	CUDA
669	CUDA0	SET_ROWS	type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1	support	0	no	CUDA
670	CUDA0	SET_ROWS	type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1	support	0	no	CUDA
671	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
672	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
673	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
674	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
675	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
676	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
677	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
678	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
679	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
680	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
681	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
682	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
683	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
684	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
685	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
686	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
687	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
688	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
689	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
690	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
691	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
692	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
693	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
694	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
695	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
696	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
697	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
698	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
699	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
700	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
701	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
702	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
703	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
704	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
705	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
706	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
707	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
708	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
709	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
710	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
711	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
712	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
713	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
714	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
715	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
716	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
717	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
718	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
719	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
720	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
721	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
722	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
723	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
724	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
725	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
726	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
727	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
728	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
729	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
730	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
731	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
732	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
733	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
734	CUDA0	POOL_2D	pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
735	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
736	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
737	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
738	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
739	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
740	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
741	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
742	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
743	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
744	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
745	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
746	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
747	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
748	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
749	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
750	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
751	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
752	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
753	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
754	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
755	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
756	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
757	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
758	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
759	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
760	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
761	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
762	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
763	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
764	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
765	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
766	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
767	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
768	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
769	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
770	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
771	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
772	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
773	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
774	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
775	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
776	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
777	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
778	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
779	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
780	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
781	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
782	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
783	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0	support	1	yes	CUDA
784	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1	support	1	yes	CUDA
785	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0	support	1	yes	CUDA
786	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1	support	1	yes	CUDA
787	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0	support	1	yes	CUDA
788	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1	support	1	yes	CUDA
789	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0	support	1	yes	CUDA
790	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1	support	1	yes	CUDA
791	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0	support	1	yes	CUDA
792	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1	support	1	yes	CUDA
793	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0	support	1	yes	CUDA
794	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1	support	1	yes	CUDA
795	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0	support	1	yes	CUDA
796	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1	support	1	yes	CUDA
797	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0	support	1	yes	CUDA
798	CUDA0	POOL_2D	pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1	support	1	yes	CUDA
799	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
800	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
801	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
802	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
803	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0	support	1	yes	CUDA
804	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
805	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0	support	1	yes	CUDA
806	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
807	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0	support	1	yes	CUDA
808	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0	support	1	yes	CUDA
809	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0	support	1	yes	CUDA
810	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
811	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
812	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
813	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
814	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
815	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
816	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
817	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
818	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
819	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
820	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
821	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
822	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
823	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
824	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
825	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
826	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
827	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
828	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
829	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
830	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
831	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
832	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
833	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
834	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
835	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
836	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
837	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
838	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
839	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
840	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
841	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
842	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
843	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
844	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
845	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
846	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
847	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
848	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
849	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
850	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
851	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
852	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
853	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
854	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
855	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
856	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
857	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
858	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
859	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
860	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
861	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
862	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
863	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
864	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
865	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
866	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
867	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
868	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
869	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
870	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
871	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
872	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
873	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
874	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1	support	1	yes	CUDA
875	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1	support	1	yes	CUDA
876	CUDA0	IM2COL	type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1	support	1	yes	CUDA
877	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
878	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
879	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
880	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
881	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
882	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
883	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
884	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
885	CUDA0	IM2COL	type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[5,5,1,32],ne_kernel=[3,4,1,32],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1	support	1	yes	CUDA
886	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
887	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
888	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
889	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
890	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
891	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
892	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
893	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
894	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
895	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
896	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
897	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
898	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
899	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
900	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
901	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
902	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
903	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
904	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
905	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
906	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
907	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
908	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
909	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
910	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
911	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
912	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
913	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
914	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
915	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
916	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
917	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
918	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
919	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
920	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
921	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
922	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
923	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
924	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
925	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
926	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
927	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
928	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
929	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
930	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
931	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
932	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
933	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
934	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
935	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
936	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
937	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
938	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
939	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
940	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
941	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
942	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
943	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
944	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
945	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
946	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
947	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
948	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
949	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
950	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
951	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
952	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
953	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
954	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
955	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
956	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
957	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
958	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
959	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
960	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
961	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
962	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
963	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
964	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
965	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
966	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
967	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
968	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
969	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
970	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
971	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
972	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
973	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
974	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
975	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
976	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
977	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
978	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
979	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
980	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
981	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
982	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
983	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
984	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
985	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
986	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
987	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
988	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
989	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
990	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
991	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
992	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
993	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
994	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
995	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
996	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
997	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
998	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
999	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1000	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1001	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1002	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1003	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1004	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1005	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1006	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1007	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1008	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1009	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1010	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1011	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1012	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1013	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1014	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1015	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1016	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1017	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1018	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1019	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1020	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1021	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1022	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1023	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1024	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1025	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1026	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1027	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1028	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1029	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1030	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1031	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1032	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1033	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1034	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1035	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1036	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1037	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1038	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1039	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1040	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1041	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1042	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1043	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1044	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1045	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1046	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1047	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1048	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1049	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1050	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1051	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1052	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1053	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1054	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1055	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1056	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1057	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1058	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1059	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1060	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1061	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1062	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1063	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1064	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1065	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1066	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1067	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1068	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1069	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1070	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1071	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1072	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1073	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1074	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1075	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1076	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1077	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1078	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1079	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1080	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1081	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1082	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1083	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1084	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1085	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1086	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1087	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1088	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1089	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1090	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1091	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1092	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1093	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1094	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1095	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1096	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1097	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1098	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1099	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1100	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1101	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1102	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1103	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1104	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1105	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1106	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1107	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1108	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1109	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1110	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1111	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1112	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1113	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1114	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1115	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1116	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1117	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1118	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1119	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1120	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1121	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1122	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1123	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1124	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1125	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1126	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1127	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1128	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1129	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1130	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1131	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1132	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1133	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1134	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1135	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1136	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1137	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1138	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1139	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1140	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1141	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1142	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1143	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1144	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1145	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1146	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1147	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1148	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1149	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1150	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1151	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1152	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1153	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1154	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1155	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1156	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1157	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1158	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1159	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1160	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1161	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1162	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1163	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1164	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1165	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1166	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1167	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1168	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1169	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1170	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1171	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1172	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1173	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1174	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1175	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1176	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1177	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1178	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1179	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1180	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1181	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1182	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1183	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1184	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1185	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1186	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1187	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1188	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1189	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1190	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1191	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1192	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1193	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1194	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1195	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1196	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1197	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1198	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1199	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1200	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1201	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1202	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1203	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1204	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1205	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1206	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1207	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1208	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1209	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1210	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1211	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1212	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1213	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1214	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1215	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1216	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1217	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1218	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1219	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1220	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1221	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1222	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1223	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1224	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1225	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1226	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1227	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1228	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1229	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1230	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1231	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1232	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1233	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1234	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1235	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1236	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1237	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1238	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1239	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1240	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1241	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1242	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1243	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1244	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1245	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1246	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1247	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1248	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1249	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1250	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1251	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1252	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1253	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1254	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1255	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1256	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1257	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1258	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1259	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1260	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1261	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1262	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1263	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1264	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1265	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1266	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1267	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1268	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1269	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1270	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1271	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1272	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1273	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1274	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1275	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1276	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1277	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1278	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1279	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1280	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1281	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1282	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1283	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1284	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1285	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1286	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1287	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1288	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1289	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1290	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1291	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1292	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1293	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1294	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1295	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1296	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1297	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1298	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1299	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1300	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1301	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1302	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1303	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1304	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1305	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1306	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1307	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1308	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1309	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1310	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1311	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1312	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1313	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1314	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1315	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1316	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1317	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1318	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1319	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1320	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1321	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1322	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1323	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1324	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1325	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1326	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1327	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1328	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1329	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1330	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1331	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1332	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1333	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1334	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1335	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1336	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1337	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1338	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1339	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1340	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1341	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1342	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1343	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1344	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1345	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1346	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1347	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1348	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1349	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1350	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1351	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1352	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1353	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1354	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1355	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1356	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1357	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1358	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1359	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1360	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1361	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1362	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1363	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1364	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1365	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1366	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1367	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1368	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1369	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1370	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1371	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1372	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1373	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1374	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1375	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1376	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1377	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1378	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1379	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1380	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1381	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1382	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1383	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1384	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1385	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1386	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1387	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1388	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1389	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1390	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1391	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1392	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1393	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1394	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1395	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1396	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1397	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1398	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1399	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1400	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1401	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1402	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1403	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1404	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1405	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1406	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1407	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1408	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1409	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1410	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1411	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1412	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1413	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1414	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1415	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1416	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1417	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1418	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1419	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1420	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1421	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1422	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1423	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1424	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1425	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1426	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1427	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1428	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1429	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1430	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1431	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1432	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1433	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1434	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1435	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1436	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1437	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1438	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1439	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1440	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1441	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1442	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1443	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1444	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1445	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1446	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1447	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1448	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1449	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1450	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1451	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1452	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1453	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1454	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1455	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1456	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1457	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1458	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1459	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1460	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1461	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1462	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1463	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1464	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1465	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1466	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1467	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1468	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1469	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1470	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1471	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1472	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1473	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1474	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1475	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1476	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1477	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1478	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1479	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1480	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1481	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1482	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1483	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1484	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1485	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1486	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1487	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1488	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1489	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1490	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1491	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1492	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1493	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1494	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1495	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1496	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1497	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1498	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1499	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1500	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1501	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1502	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1503	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1504	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1505	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1506	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1507	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1508	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1509	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1510	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1511	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1512	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1513	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1514	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1515	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1516	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1517	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1518	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1519	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1520	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1521	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1522	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1523	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1524	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1525	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1526	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1527	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1528	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1529	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1530	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1531	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1532	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1533	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1534	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1535	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1536	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1537	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1538	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1539	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1540	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1541	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1542	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1543	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1544	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1545	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1546	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1547	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1548	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1549	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1550	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1551	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1552	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1553	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1554	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1555	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1556	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1557	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1558	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1559	CUDA0	CONV_2D	ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1560	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1561	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1562	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1563	CUDA0	CONV_2D	ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1564	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1565	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1566	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1567	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1568	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1569	CUDA0	CONV_2D	ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1570	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1571	CUDA0	CONV_2D	ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1572	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1573	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1574	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1575	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1576	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1577	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1578	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1579	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1580	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1581	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1582	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1583	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1584	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1585	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1586	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1587	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1588	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1589	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1590	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1591	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1592	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1593	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1594	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1595	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1596	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1597	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1598	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1599	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1600	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1601	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1602	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1603	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1604	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1605	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1606	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1607	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1608	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1609	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1610	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1611	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1612	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1613	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1614	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1615	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1616	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1617	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1618	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1619	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1620	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1621	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1622	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1623	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1624	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1625	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1626	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1627	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1628	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1629	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1630	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1631	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1632	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1633	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1634	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1635	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1636	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1637	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1638	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1639	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1640	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1641	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1642	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1643	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1644	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1645	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1646	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1647	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1648	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1649	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1650	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1651	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1652	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1653	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1654	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1655	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1656	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1657	CUDA0	CONV_2D	ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1658	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1659	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1660	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1661	CUDA0	CONV_2D	ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1662	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1663	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1664	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1665	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1666	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1667	CUDA0	CONV_2D	ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1668	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1669	CUDA0	CONV_2D	ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0	support	0	no	CUDA
1670	CUDA0	CONV_2D_DW	ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0	support	1	yes	CUDA
1671	CUDA0	CONV_2D_DW	ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1	support	1	yes	CUDA
1672	CUDA0	CONV_2D_DW	ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0	support	1	yes	CUDA
1673	CUDA0	CONV_2D_DW	ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1	support	1	yes	CUDA
1674	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1675	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1676	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1677	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1678	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1679	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1680	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1681	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1682	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1683	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1684	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1685	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1686	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1687	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1688	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1689	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1690	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1691	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1692	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1693	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1694	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1695	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1696	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1697	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1698	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1699	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1700	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1701	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1702	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1703	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1704	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1705	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1706	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1707	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1708	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1709	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1710	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1711	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1712	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1713	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1714	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1715	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1716	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1717	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1718	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1719	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1720	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1721	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1722	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1723	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1724	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1725	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1726	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1727	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1728	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1729	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1730	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1731	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1732	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1733	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1734	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1735	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1736	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1737	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1738	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1739	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1740	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1741	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1742	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1743	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1744	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1745	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1746	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1747	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1748	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1749	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1750	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1751	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1752	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1753	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1754	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1755	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1756	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1757	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1758	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1759	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1760	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1761	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1762	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1763	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1764	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1765	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1766	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1767	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1768	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1769	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1770	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1771	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1772	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1773	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1774	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1775	CUDA0	CONV_TRANSPOSE_1D	ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1776	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1777	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1778	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1779	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1780	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1781	CUDA0	CONV_TRANSPOSE_1D	ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1782	CUDA0	CONV_TRANSPOSE_1D	ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1783	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1	support	1	yes	CUDA
1784	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1785	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1786	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1	support	1	yes	CUDA
1787	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1788	CUDA0	CONV_TRANSPOSE_1D	ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1789	CUDA0	CONV_TRANSPOSE_1D	ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1	support	1	yes	CUDA
1790	CUDA0	CONV_TRANSPOSE_2D	ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1	support	1	yes	CUDA
1791	CUDA0	CONV_TRANSPOSE_2D	ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2	support	1	yes	CUDA
1792	CUDA0	COUNT_EQUAL	type=f32,ne=[4,500,1,1]	support	1	yes	CUDA
1793	CUDA0	COUNT_EQUAL	type=f32,ne=[4,5000,1,1]	support	1	yes	CUDA
1794	CUDA0	ARGMAX	type=f32,ne=[32,1,1,1]	support	1	yes	CUDA
1795	CUDA0	ARGMAX	type=f32,ne=[100,10,1,1]	support	1	yes	CUDA
1796	CUDA0	ARGMAX	type=f32,ne=[1024,10,1,1]	support	1	yes	CUDA
1797	CUDA0	ARGMAX	type=f32,ne=[1024,12,1,1]	support	1	yes	CUDA
1798	CUDA0	ARGMAX	type=f32,ne=[2000,10,1,1]	support	1	yes	CUDA
1799	CUDA0	ARGMAX	type=f32,ne=[5438,3,1,1]	support	1	yes	CUDA
1800	CUDA0	REPEAT	type=f32,ne=[10,5,4,1],nr=[1,1,1,1]	support	1	yes	CUDA
1801	CUDA0	REPEAT	type=f32,ne=[10,5,4,1],nr=[2,1,1,1]	support	1	yes	CUDA
1802	CUDA0	REPEAT	type=f32,ne=[10,5,4,1],nr=[1,2,1,1]	support	1	yes	CUDA
1803	CUDA0	REPEAT	type=f32,ne=[10,5,4,1],nr=[1,1,2,1]	support	1	yes	CUDA
1804	CUDA0	REPEAT	type=f32,ne=[10,5,4,1],nr=[1,1,1,2]	support	1	yes	CUDA
1805	CUDA0	REPEAT	type=i32,ne=[10,5,4,1],nr=[2,1,1,1]	support	0	no	CUDA
1806	CUDA0	REPEAT	type=i16,ne=[10,5,4,1],nr=[1,1,1,2]	support	0	no	CUDA
1807	CUDA0	REPEAT	type=f32,ne=[10,5,4,3],nr=[1,1,1,1]	support	1	yes	CUDA
1808	CUDA0	REPEAT	type=f32,ne=[10,5,4,3],nr=[2,1,1,1]	support	1	yes	CUDA
1809	CUDA0	REPEAT	type=f32,ne=[10,5,4,3],nr=[1,2,1,1]	support	1	yes	CUDA
1810	CUDA0	REPEAT	type=f32,ne=[10,5,4,3],nr=[1,1,2,1]	support	1	yes	CUDA
1811	CUDA0	REPEAT	type=f32,ne=[10,5,4,3],nr=[1,1,1,2]	support	1	yes	CUDA
1812	CUDA0	REPEAT	type=i32,ne=[10,5,4,3],nr=[2,1,1,1]	support	0	no	CUDA
1813	CUDA0	REPEAT	type=i16,ne=[10,5,4,3],nr=[1,1,1,2]	support	0	no	CUDA
1814	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0	support	1	yes	CUDA
1815	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0	support	1	yes	CUDA
1816	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0	support	1	yes	CUDA
1817	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0	support	1	yes	CUDA
1818	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0	support	1	yes	CUDA
1819	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1	support	1	yes	CUDA
1820	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1	support	1	yes	CUDA
1821	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1	support	1	yes	CUDA
1822	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1	support	1	yes	CUDA
1823	CUDA0	REPEAT_BACK	type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1	support	1	yes	CUDA
1824	CUDA0	DUP	type=f32,ne=[10,10,20,1]	support	1	yes	CUDA
1825	CUDA0	DUP	type=f16,ne=[10,10,20,1]	support	1	yes	CUDA
1826	CUDA0	DUP	type=i32,ne=[10,10,20,1]	support	0	no	CUDA
1827	CUDA0	DUP	type=i16,ne=[10,10,20,1]	support	0	no	CUDA
1828	CUDA0	DUP	type=f32,ne=[10,10,5,1],permute=[0,2,1,3]	support	1	yes	CUDA
1829	CUDA0	DUP	type=f16,ne=[10,10,5,1],permute=[0,2,1,3]	support	1	yes	CUDA
1830	CUDA0	DUP	type=f32,ne=[10,10,5,1],permute=[1,0,2,3]	support	1	yes	CUDA
1831	CUDA0	DUP	type=f16,ne=[10,10,5,1],permute=[1,0,2,3]	support	1	yes	CUDA
1832	CUDA0	DUP	type=i16,ne=[10,8,3,1],permute=[0,2,1,3]	support	0	no	CUDA
1833	CUDA0	DUP	type=i16,ne=[10,8,3,1],permute=[1,2,0,3]	support	0	no	CUDA
1834	CUDA0	SET	type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1	support	0	no	CUDA
1835	CUDA0	SET	type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2	support	0	no	CUDA
1836	CUDA0	SET	type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3	support	0	no	CUDA
1837	CUDA0	SET	type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1	support	0	no	CUDA
1838	CUDA0	SET	type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2	support	0	no	CUDA
1839	CUDA0	SET	type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3	support	0	no	CUDA
1840	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1841	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1842	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1843	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1844	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1845	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1846	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1847	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1848	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1849	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1850	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1851	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1852	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1853	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1854	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1855	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1856	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1857	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1858	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1859	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1860	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1861	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1862	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1863	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1864	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1865	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1866	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	1	yes	CUDA
1867	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1868	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1869	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1870	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1871	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1872	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1873	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1874	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1875	CUDA0	CPY	type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1876	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1877	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1878	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1879	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1880	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1881	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1882	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1883	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1884	CUDA0	CPY	type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1885	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1886	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1887	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1888	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1889	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1890	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1891	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1892	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1893	CUDA0	CPY	type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1894	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1895	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1896	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1897	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1898	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1899	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1900	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1901	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1902	CUDA0	CPY	type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1903	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1904	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1905	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1906	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1907	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1908	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1909	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1910	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1911	CUDA0	CPY	type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1912	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1913	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1914	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1915	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1916	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1917	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1918	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1919	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1920	CUDA0	CPY	type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1921	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1922	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1923	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1924	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1925	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1926	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1927	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1928	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1929	CUDA0	CPY	type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1930	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1931	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1932	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1933	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1934	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1935	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1936	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1937	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1938	CUDA0	CPY	type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1939	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1940	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1941	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1942	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1943	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1944	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1945	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1946	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1947	CUDA0	CPY	type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1948	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1949	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1950	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1951	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1952	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1953	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1954	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1955	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1956	CUDA0	CPY	type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1957	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1958	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1959	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1960	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1961	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1962	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1963	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1964	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1965	CUDA0	CPY	type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1966	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1967	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1968	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1969	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1970	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1971	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1972	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1973	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1974	CUDA0	CPY	type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1975	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1976	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1977	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1978	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1979	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1980	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1981	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1982	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1983	CUDA0	CPY	type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1984	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1985	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1986	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1987	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1988	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1989	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1990	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1991	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1992	CUDA0	CPY	type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1993	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1994	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1995	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1996	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
1997	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
1998	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
1999	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2000	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2001	CUDA0	CPY	type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2002	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2003	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2004	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2005	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2006	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2007	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2008	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2009	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2010	CUDA0	CPY	type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2011	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2012	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2013	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2014	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2015	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2016	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2017	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2018	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2019	CUDA0	CPY	type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2020	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2021	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2022	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2023	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2024	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2025	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2026	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2027	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2028	CUDA0	CPY	type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2029	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2030	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2031	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2032	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2033	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2034	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2035	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2036	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2037	CUDA0	CPY	type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3]	support	0	no	CUDA
2038	CUDA0	CPY	type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2039	CUDA0	CPY	type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2040	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2041	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2042	CUDA0	CPY	type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2043	CUDA0	CPY	type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2044	CUDA0	CPY	type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2045	CUDA0	CPY	type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2046	CUDA0	CPY	type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2047	CUDA0	CPY	type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2048	CUDA0	CPY	type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2049	CUDA0	CPY	type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2050	CUDA0	CPY	type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2051	CUDA0	CPY	type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2052	CUDA0	CPY	type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2053	CUDA0	CPY	type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2054	CUDA0	CPY	type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2055	CUDA0	CPY	type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2056	CUDA0	CPY	type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2057	CUDA0	CPY	type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2058	CUDA0	CPY	type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2059	CUDA0	CPY	type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2060	CUDA0	CPY	type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2061	CUDA0	CPY	type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2062	CUDA0	CPY	type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2063	CUDA0	CPY	type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2064	CUDA0	CPY	type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2065	CUDA0	CPY	type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2066	CUDA0	CPY	type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2067	CUDA0	CPY	type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2068	CUDA0	CPY	type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2069	CUDA0	CPY	type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2070	CUDA0	CPY	type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2071	CUDA0	CPY	type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2072	CUDA0	CPY	type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2073	CUDA0	CPY	type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2074	CUDA0	CPY	type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2075	CUDA0	CPY	type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2076	CUDA0	CPY	type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2077	CUDA0	CPY	type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2078	CUDA0	CPY	type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2079	CUDA0	CPY	type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2080	CUDA0	CPY	type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2081	CUDA0	CPY	type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2082	CUDA0	CPY	type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2083	CUDA0	CPY	type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2084	CUDA0	CPY	type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2085	CUDA0	CPY	type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2086	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2087	CUDA0	CPY	type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2088	CUDA0	CPY	type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2089	CUDA0	CPY	type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2090	CUDA0	CPY	type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2091	CUDA0	CPY	type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2092	CUDA0	CPY	type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2093	CUDA0	CPY	type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2094	CUDA0	CPY	type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2095	CUDA0	CPY	type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2096	CUDA0	CPY	type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2097	CUDA0	CPY	type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2098	CUDA0	CPY	type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2099	CUDA0	CPY	type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2100	CUDA0	CPY	type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2101	CUDA0	CPY	type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2102	CUDA0	CPY	type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2103	CUDA0	CPY	type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2104	CUDA0	CPY	type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2105	CUDA0	CPY	type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2106	CUDA0	CPY	type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2107	CUDA0	CPY	type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2108	CUDA0	CPY	type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2109	CUDA0	CPY	type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2110	CUDA0	CPY	type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2111	CUDA0	CPY	type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2112	CUDA0	CPY	type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2113	CUDA0	CPY	type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2114	CUDA0	CPY	type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2115	CUDA0	CPY	type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2116	CUDA0	CPY	type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2117	CUDA0	CPY	type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2118	CUDA0	CPY	type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2119	CUDA0	CPY	type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2120	CUDA0	CPY	type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2121	CUDA0	CPY	type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2122	CUDA0	CPY	type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2123	CUDA0	CPY	type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2124	CUDA0	CPY	type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2125	CUDA0	CPY	type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2126	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2127	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2128	CUDA0	CPY	type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2129	CUDA0	CPY	type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2130	CUDA0	CPY	type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2131	CUDA0	CPY	type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2132	CUDA0	CPY	type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2133	CUDA0	CPY	type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2134	CUDA0	CPY	type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2135	CUDA0	CPY	type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2136	CUDA0	CPY	type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2137	CUDA0	CPY	type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2138	CUDA0	CPY	type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2139	CUDA0	CPY	type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2140	CUDA0	CPY	type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2141	CUDA0	CPY	type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2142	CUDA0	CPY	type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2143	CUDA0	CPY	type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2144	CUDA0	CPY	type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2145	CUDA0	CPY	type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2146	CUDA0	CPY	type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2147	CUDA0	CPY	type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2148	CUDA0	CPY	type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2149	CUDA0	CPY	type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2150	CUDA0	CPY	type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2151	CUDA0	CPY	type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2152	CUDA0	CPY	type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2153	CUDA0	CPY	type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2154	CUDA0	CPY	type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2155	CUDA0	CPY	type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2156	CUDA0	CPY	type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2157	CUDA0	CPY	type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2158	CUDA0	CPY	type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2159	CUDA0	CPY	type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2160	CUDA0	CPY	type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2161	CUDA0	CPY	type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2162	CUDA0	CPY	type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2163	CUDA0	CPY	type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2164	CUDA0	CPY	type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2165	CUDA0	CPY	type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2166	CUDA0	CPY	type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2167	CUDA0	CPY	type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2168	CUDA0	CPY	type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2169	CUDA0	CPY	type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2170	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2171	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2172	CUDA0	CPY	type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2173	CUDA0	CPY	type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2174	CUDA0	CPY	type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2175	CUDA0	CPY	type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2176	CUDA0	CPY	type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2177	CUDA0	CPY	type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2178	CUDA0	CPY	type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2179	CUDA0	CPY	type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2180	CUDA0	CPY	type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2181	CUDA0	CPY	type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2182	CUDA0	CPY	type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2183	CUDA0	CPY	type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2184	CUDA0	CPY	type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2185	CUDA0	CPY	type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2186	CUDA0	CPY	type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2187	CUDA0	CPY	type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2188	CUDA0	CPY	type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2189	CUDA0	CPY	type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2190	CUDA0	CPY	type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2191	CUDA0	CPY	type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2192	CUDA0	CPY	type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2193	CUDA0	CPY	type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2194	CUDA0	CPY	type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2195	CUDA0	CPY	type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2196	CUDA0	CPY	type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2197	CUDA0	CPY	type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2198	CUDA0	CPY	type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2199	CUDA0	CPY	type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2200	CUDA0	CPY	type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2201	CUDA0	CPY	type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2202	CUDA0	CPY	type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2203	CUDA0	CPY	type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2204	CUDA0	CPY	type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2205	CUDA0	CPY	type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2206	CUDA0	CPY	type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2207	CUDA0	CPY	type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2208	CUDA0	CPY	type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2209	CUDA0	CPY	type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2210	CUDA0	CPY	type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2211	CUDA0	CPY	type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2212	CUDA0	CPY	type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0]	support	0	no	CUDA
2213	CUDA0	CPY	type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0]	support	0	no	CUDA
2214	CUDA0	CPY	type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2215	CUDA0	CPY	type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2216	CUDA0	CPY	type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2217	CUDA0	CPY	type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0]	support	1	yes	CUDA
2218	CUDA0	CONT	type=f32,ne=[10,10,10,1]	support	1	yes	CUDA
2219	CUDA0	CONT	type=f32,ne=[2,1,1,1]	support	1	yes	CUDA
2220	CUDA0	CONT	type=f32,ne=[2,1,3,5]	support	1	yes	CUDA
2221	CUDA0	CONT	type=f32,ne=[2,3,5,7]	support	1	yes	CUDA
2222	CUDA0	CONT	type=f16,ne=[2,1,1,1]	support	1	yes	CUDA
2223	CUDA0	CONT	type=f16,ne=[2,1,3,5]	support	1	yes	CUDA
2224	CUDA0	CONT	type=f16,ne=[2,3,5,7]	support	1	yes	CUDA
2225	CUDA0	CONT	type=bf16,ne=[2,1,1,1]	support	1	yes	CUDA
2226	CUDA0	CONT	type=bf16,ne=[2,1,3,5]	support	1	yes	CUDA
2227	CUDA0	CONT	type=bf16,ne=[2,3,5,7]	support	1	yes	CUDA
2228	CUDA0	ADD	type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2229	CUDA0	SUB	type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2230	CUDA0	MUL	type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2231	CUDA0	DIV	type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2232	CUDA0	ADD	type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2233	CUDA0	SUB	type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2234	CUDA0	MUL	type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2235	CUDA0	DIV	type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2236	CUDA0	ADD	type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2237	CUDA0	SUB	type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2238	CUDA0	MUL	type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2239	CUDA0	DIV	type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2240	CUDA0	ADD	type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2241	CUDA0	SUB	type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2242	CUDA0	MUL	type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2243	CUDA0	DIV	type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2244	CUDA0	ADD	type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2245	CUDA0	SUB	type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2246	CUDA0	MUL	type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2247	CUDA0	DIV	type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2248	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2249	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2250	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2251	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2252	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2253	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2254	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2255	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2256	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2257	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2258	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2259	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2260	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2261	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2262	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2263	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2264	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2265	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2266	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2267	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2268	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2269	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2270	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2271	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2272	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2273	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2274	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2275	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2276	CUDA0	ADD	type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2277	CUDA0	SUB	type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2278	CUDA0	MUL	type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2279	CUDA0	DIV	type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2280	CUDA0	ADD	type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2281	CUDA0	SUB	type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2282	CUDA0	MUL	type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2283	CUDA0	DIV	type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2284	CUDA0	ADD	type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2285	CUDA0	SUB	type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2286	CUDA0	MUL	type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2287	CUDA0	DIV	type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2288	CUDA0	ADD	type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2289	CUDA0	SUB	type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2290	CUDA0	MUL	type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2291	CUDA0	DIV	type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2292	CUDA0	ADD	type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2293	CUDA0	SUB	type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2294	CUDA0	MUL	type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2295	CUDA0	DIV	type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2296	CUDA0	ADD	type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2297	CUDA0	SUB	type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2298	CUDA0	MUL	type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2299	CUDA0	DIV	type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2300	CUDA0	ADD	type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2301	CUDA0	SUB	type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2302	CUDA0	MUL	type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2303	CUDA0	DIV	type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2304	CUDA0	ADD	type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2305	CUDA0	SUB	type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2306	CUDA0	MUL	type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2307	CUDA0	DIV	type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2308	CUDA0	ADD	type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2309	CUDA0	SUB	type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2310	CUDA0	MUL	type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2311	CUDA0	DIV	type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2312	CUDA0	ADD	type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2313	CUDA0	SUB	type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2314	CUDA0	MUL	type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2315	CUDA0	DIV	type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2316	CUDA0	ADD	type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2317	CUDA0	SUB	type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2318	CUDA0	MUL	type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2319	CUDA0	DIV	type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2320	CUDA0	ADD	type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2321	CUDA0	SUB	type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2322	CUDA0	MUL	type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2323	CUDA0	DIV	type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2324	CUDA0	ADD	type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2325	CUDA0	SUB	type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2326	CUDA0	MUL	type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2327	CUDA0	DIV	type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2328	CUDA0	ADD	type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2329	CUDA0	SUB	type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2330	CUDA0	MUL	type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2331	CUDA0	DIV	type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2332	CUDA0	ADD	type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2333	CUDA0	SUB	type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2334	CUDA0	MUL	type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2335	CUDA0	DIV	type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2336	CUDA0	ADD	type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2337	CUDA0	SUB	type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2338	CUDA0	MUL	type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2339	CUDA0	DIV	type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1	support	1	yes	CUDA
2340	CUDA0	ADD	type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2341	CUDA0	SUB	type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2342	CUDA0	MUL	type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2343	CUDA0	DIV	type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2344	CUDA0	ADD	type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2345	CUDA0	SUB	type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2346	CUDA0	MUL	type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2347	CUDA0	DIV	type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2348	CUDA0	ADD	type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2349	CUDA0	SUB	type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2350	CUDA0	MUL	type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2351	CUDA0	DIV	type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2352	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2353	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2354	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2355	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2356	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2357	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2358	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2359	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1	support	1	yes	CUDA
2360	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2361	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2362	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2363	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1	support	1	yes	CUDA
2364	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2365	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2366	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2367	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1	support	1	yes	CUDA
2368	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2369	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2370	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2371	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1	support	1	yes	CUDA
2372	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2373	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2374	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2375	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1	support	1	yes	CUDA
2376	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2377	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2378	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2379	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1	support	1	yes	CUDA
2380	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2381	CUDA0	SUB	type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2382	CUDA0	MUL	type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2383	CUDA0	DIV	type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1	support	1	yes	CUDA
2384	CUDA0	ADD	type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2385	CUDA0	SUB	type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2386	CUDA0	MUL	type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2387	CUDA0	DIV	type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2388	CUDA0	ADD	type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2389	CUDA0	SUB	type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2390	CUDA0	MUL	type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2391	CUDA0	DIV	type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1	support	1	yes	CUDA
2392	CUDA0	ADD	type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2393	CUDA0	SUB	type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2394	CUDA0	MUL	type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2395	CUDA0	DIV	type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2396	CUDA0	ADD	type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2397	CUDA0	SUB	type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2398	CUDA0	MUL	type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2399	CUDA0	DIV	type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2400	CUDA0	ADD	type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2401	CUDA0	SUB	type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2402	CUDA0	MUL	type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2403	CUDA0	DIV	type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2404	CUDA0	ADD	type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2405	CUDA0	SUB	type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2406	CUDA0	MUL	type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2407	CUDA0	DIV	type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2408	CUDA0	ADD	type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2409	CUDA0	SUB	type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2410	CUDA0	MUL	type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2411	CUDA0	DIV	type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2412	CUDA0	ADD	type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2413	CUDA0	SUB	type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2414	CUDA0	MUL	type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2415	CUDA0	DIV	type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1	support	1	yes	CUDA
2416	CUDA0	ADD	type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2417	CUDA0	SUB	type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2418	CUDA0	MUL	type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2419	CUDA0	DIV	type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2420	CUDA0	ADD	type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2421	CUDA0	SUB	type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2422	CUDA0	MUL	type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2423	CUDA0	DIV	type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2424	CUDA0	ADD	type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2425	CUDA0	SUB	type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2426	CUDA0	MUL	type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2427	CUDA0	DIV	type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1	support	1	yes	CUDA
2428	CUDA0	ADD	type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2429	CUDA0	SUB	type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2430	CUDA0	MUL	type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2431	CUDA0	DIV	type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1	support	1	yes	CUDA
2432	CUDA0	ADD	type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2433	CUDA0	SUB	type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2434	CUDA0	MUL	type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2435	CUDA0	DIV	type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1	support	1	yes	CUDA
2436	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=2	support	1	yes	CUDA
2437	CUDA0	ADD	type=f32,ne=[16,5,4,3],nr=[1,2,1,1],nf=3	support	1	yes	CUDA
2438	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=4	support	1	yes	CUDA
2439	CUDA0	ADD	type=f32,ne=[16,5,4,3],nr=[1,1,1,2],nf=5	support	1	yes	CUDA
2440	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=6	support	1	yes	CUDA
2441	CUDA0	ADD	type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=7	support	1	yes	CUDA
2442	CUDA0	ADD	type=f32,ne=[16,5,4,3],nr=[2,2,2,2],nf=8	support	1	yes	CUDA
2443	CUDA0	ADD1	type=f32,ne=[10,5,4,3]	support	1	yes	CUDA
2444	CUDA0	SCALE	type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000	support	1	yes	CUDA
2445	CUDA0	SCALE	type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000	support	1	yes	CUDA
2446	CUDA0	SILU_BACK	type=f32,ne=[64,5,4,3],eps=0.000001	support	1	yes	CUDA
2447	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000000	support	1	yes	CUDA
2448	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000000	support	1	yes	CUDA
2449	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000000	support	1	yes	CUDA
2450	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000000	support	1	yes	CUDA
2451	CUDA0	RMS_NORM_BACK	type=f32,ne=[64,5,4,3],eps=0.000000	support	1	yes	CUDA
2452	CUDA0	L2_NORM	type=f32,ne=[64,5,4,3]	support	1	yes	CUDA
2453	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000001	support	1	yes	CUDA
2454	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000001	support	1	yes	CUDA
2455	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000001	support	1	yes	CUDA
2456	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000001	support	1	yes	CUDA
2457	CUDA0	RMS_NORM_BACK	type=f32,ne=[64,5,4,3],eps=0.000001	support	1	yes	CUDA
2458	CUDA0	L2_NORM	type=f32,ne=[64,5,4,3]	support	1	yes	CUDA
2459	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000100	support	1	yes	CUDA
2460	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.000100	support	1	yes	CUDA
2461	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000100	support	1	yes	CUDA
2462	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.000100	support	1	yes	CUDA
2463	CUDA0	RMS_NORM_BACK	type=f32,ne=[64,5,4,3],eps=0.000100	support	1	yes	CUDA
2464	CUDA0	L2_NORM	type=f32,ne=[64,5,4,3]	support	1	yes	CUDA
2465	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.100000	support	1	yes	CUDA
2466	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=0,eps=0.100000	support	1	yes	CUDA
2467	CUDA0	NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.100000	support	1	yes	CUDA
2468	CUDA0	RMS_NORM	type=f32,ne=[64,5,4,3],v=1,eps=0.100000	support	1	yes	CUDA
2469	CUDA0	RMS_NORM_BACK	type=f32,ne=[64,5,4,3],eps=0.100000	support	1	yes	CUDA
2470	CUDA0	L2_NORM	type=f32,ne=[64,5,4,3]	support	1	yes	CUDA
2471	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=0	support	1	yes	CUDA
2472	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=1	support	1	yes	CUDA
2473	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=0	support	1	yes	CUDA
2474	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=1	support	1	yes	CUDA
2475	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=0	support	1	yes	CUDA
2476	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=1	support	1	yes	CUDA
2477	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=0	support	1	yes	CUDA
2478	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=1	support	1	yes	CUDA
2479	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=0	support	1	yes	CUDA
2480	CUDA0	RMS_NORM_MUL_ADD	type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=1	support	1	yes	CUDA
2481	CUDA0	L2_NORM	type=f32,ne=[64,5,4,3]	support	1	yes	CUDA
2482	CUDA0	SSM_CONV	type=f32,ne_a=[4,1024,1,1],ne_b=[3,1024,1,1]	support	1	yes	CUDA
2483	CUDA0	SSM_CONV	type=f32,ne_a=[8,1024,1,1],ne_b=[3,1024,1,1]	support	1	yes	CUDA
2484	CUDA0	SSM_CONV	type=f32,ne_a=[4,1024,4,1],ne_b=[3,1024,1,1]	support	1	yes	CUDA
2485	CUDA0	SSM_CONV	type=f32,ne_a=[4,1536,1,1],ne_b=[3,1536,1,1]	support	1	yes	CUDA
2486	CUDA0	SSM_CONV	type=f32,ne_a=[8,1536,1,1],ne_b=[3,1536,1,1]	support	1	yes	CUDA
2487	CUDA0	SSM_CONV	type=f32,ne_a=[4,1536,4,1],ne_b=[3,1536,1,1]	support	1	yes	CUDA
2488	CUDA0	SSM_CONV	type=f32,ne_a=[4,2048,1,1],ne_b=[3,2048,1,1]	support	1	yes	CUDA
2489	CUDA0	SSM_CONV	type=f32,ne_a=[8,2048,1,1],ne_b=[3,2048,1,1]	support	1	yes	CUDA
2490	CUDA0	SSM_CONV	type=f32,ne_a=[4,2048,4,1],ne_b=[3,2048,1,1]	support	1	yes	CUDA
2491	CUDA0	SSM_CONV	type=f32,ne_a=[4,1024,1,1],ne_b=[4,1024,1,1]	support	1	yes	CUDA
2492	CUDA0	SSM_CONV	type=f32,ne_a=[8,1024,1,1],ne_b=[4,1024,1,1]	support	1	yes	CUDA
2493	CUDA0	SSM_CONV	type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1]	support	1	yes	CUDA
2494	CUDA0	SSM_CONV	type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1]	support	1	yes	CUDA
2495	CUDA0	SSM_CONV	type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1]	support	1	yes	CUDA
2496	CUDA0	SSM_CONV	type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1]	support	1	yes	CUDA
2497	CUDA0	SSM_CONV	type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1]	support	1	yes	CUDA
2498	CUDA0	SSM_CONV	type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1]	support	1	yes	CUDA
2499	CUDA0	SSM_CONV	type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1]	support	1	yes	CUDA
2500	CUDA0	SSM_SCAN	type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4	support	1	yes	CUDA

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