mirror of
https://github.com/ggml-org/llama.cpp.git
synced 2025-08-04 08:15:55 -04:00
984 KiB
984 KiB
1 | backend_name | op_name | op_params | test_mode | supported | error_message | backend_reg_name |
---|---|---|---|---|---|---|---|
2 | CPU | ABS | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
3 | CPU | ABS | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
4 | CPU | SGN | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
5 | CPU | SGN | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
6 | CPU | NEG | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
7 | CPU | NEG | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
8 | CPU | STEP | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
9 | CPU | STEP | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
10 | CPU | TANH | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
11 | CPU | TANH | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
12 | CPU | ELU | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
13 | CPU | ELU | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
14 | CPU | RELU | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
15 | CPU | RELU | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
16 | CPU | SIGMOID | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
17 | CPU | SIGMOID | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
18 | CPU | GELU | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
19 | CPU | GELU | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
20 | CPU | GELU_QUICK | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
21 | CPU | GELU_QUICK | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
22 | CPU | SILU | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
23 | CPU | SILU | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
24 | CPU | HARDSWISH | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
25 | CPU | HARDSWISH | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
26 | CPU | HARDSIGMOID | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
27 | CPU | HARDSIGMOID | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
28 | CPU | EXP | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
29 | CPU | EXP | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
30 | CPU | GELU_ERF | type=f16,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
31 | CPU | GELU_ERF | type=f16,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
32 | CPU | ABS | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
33 | CPU | ABS | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
34 | CPU | SGN | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
35 | CPU | SGN | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
36 | CPU | NEG | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
37 | CPU | NEG | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
38 | CPU | STEP | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
39 | CPU | STEP | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
40 | CPU | TANH | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
41 | CPU | TANH | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
42 | CPU | ELU | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
43 | CPU | ELU | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
44 | CPU | RELU | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
45 | CPU | RELU | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
46 | CPU | SIGMOID | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
47 | CPU | SIGMOID | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
48 | CPU | GELU | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
49 | CPU | GELU | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
50 | CPU | GELU_QUICK | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
51 | CPU | GELU_QUICK | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
52 | CPU | SILU | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
53 | CPU | SILU | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
54 | CPU | HARDSWISH | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
55 | CPU | HARDSWISH | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
56 | CPU | HARDSIGMOID | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
57 | CPU | HARDSIGMOID | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
58 | CPU | EXP | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
59 | CPU | EXP | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
60 | CPU | GELU_ERF | type=f16,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
61 | CPU | GELU_ERF | type=f16,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
62 | CPU | ABS | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
63 | CPU | ABS | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
64 | CPU | SGN | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
65 | CPU | SGN | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
66 | CPU | NEG | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
67 | CPU | NEG | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
68 | CPU | STEP | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
69 | CPU | STEP | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
70 | CPU | TANH | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
71 | CPU | TANH | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
72 | CPU | ELU | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
73 | CPU | ELU | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
74 | CPU | RELU | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
75 | CPU | RELU | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
76 | CPU | SIGMOID | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
77 | CPU | SIGMOID | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
78 | CPU | GELU | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
79 | CPU | GELU | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
80 | CPU | GELU_QUICK | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
81 | CPU | GELU_QUICK | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
82 | CPU | SILU | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
83 | CPU | SILU | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
84 | CPU | HARDSWISH | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
85 | CPU | HARDSWISH | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
86 | CPU | HARDSIGMOID | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
87 | CPU | HARDSIGMOID | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
88 | CPU | EXP | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
89 | CPU | EXP | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
90 | CPU | GELU_ERF | type=f32,ne_a=[128,2,2,2],v=0 | support | 1 | yes | CPU |
91 | CPU | GELU_ERF | type=f32,ne_a=[5,7,11,13],v=0 | support | 1 | yes | CPU |
92 | CPU | ABS | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
93 | CPU | ABS | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
94 | CPU | SGN | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
95 | CPU | SGN | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
96 | CPU | NEG | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
97 | CPU | NEG | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
98 | CPU | STEP | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
99 | CPU | STEP | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
100 | CPU | TANH | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
101 | CPU | TANH | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
102 | CPU | ELU | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
103 | CPU | ELU | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
104 | CPU | RELU | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
105 | CPU | RELU | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
106 | CPU | SIGMOID | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
107 | CPU | SIGMOID | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
108 | CPU | GELU | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
109 | CPU | GELU | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
110 | CPU | GELU_QUICK | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
111 | CPU | GELU_QUICK | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
112 | CPU | SILU | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
113 | CPU | SILU | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
114 | CPU | HARDSWISH | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
115 | CPU | HARDSWISH | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
116 | CPU | HARDSIGMOID | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
117 | CPU | HARDSIGMOID | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
118 | CPU | EXP | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
119 | CPU | EXP | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
120 | CPU | GELU_ERF | type=f32,ne_a=[128,2,2,2],v=1 | support | 1 | yes | CPU |
121 | CPU | GELU_ERF | type=f32,ne_a=[5,7,11,13],v=1 | support | 1 | yes | CPU |
122 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
123 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
124 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
125 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
126 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
127 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
128 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
129 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
130 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
131 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
132 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
133 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
134 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
135 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
136 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
137 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
138 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
139 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
140 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
141 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
142 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
143 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
144 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
145 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
146 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
147 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
148 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
149 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
150 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
151 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
152 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
153 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
154 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
155 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
156 | CPU | REGLU | type=f16,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
157 | CPU | REGLU | type=f16,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
158 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
159 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
160 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
161 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
162 | CPU | GEGLU | type=f16,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
163 | CPU | GEGLU | type=f16,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
164 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
165 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
166 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
167 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
168 | CPU | SWIGLU | type=f16,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
169 | CPU | SWIGLU | type=f16,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
170 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
171 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
172 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
173 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
174 | CPU | GEGLU_ERF | type=f16,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
175 | CPU | GEGLU_ERF | type=f16,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
176 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
177 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
178 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
179 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
180 | CPU | GEGLU_QUICK | type=f16,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
181 | CPU | GEGLU_QUICK | type=f16,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
182 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
183 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
184 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
185 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
186 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
187 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
188 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
189 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
190 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
191 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
192 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
193 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
194 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
195 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
196 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
197 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
198 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
199 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
200 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
201 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
202 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
203 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
204 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
205 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
206 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=0,swapped=0 | support | 1 | yes | CPU |
207 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=0,swapped=0 | support | 1 | yes | CPU |
208 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=0,swapped=1 | support | 1 | yes | CPU |
209 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=0,swapped=1 | support | 1 | yes | CPU |
210 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=0,split | support | 1 | yes | CPU |
211 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=0,split | support | 1 | yes | CPU |
212 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
213 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
214 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
215 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
216 | CPU | REGLU | type=f32,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
217 | CPU | REGLU | type=f32,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
218 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
219 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
220 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
221 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
222 | CPU | GEGLU | type=f32,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
223 | CPU | GEGLU | type=f32,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
224 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
225 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
226 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
227 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
228 | CPU | SWIGLU | type=f32,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
229 | CPU | SWIGLU | type=f32,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
230 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
231 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
232 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
233 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
234 | CPU | GEGLU_ERF | type=f32,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
235 | CPU | GEGLU_ERF | type=f32,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
236 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=1,swapped=0 | support | 1 | yes | CPU |
237 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=1,swapped=0 | support | 1 | yes | CPU |
238 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=1,swapped=1 | support | 1 | yes | CPU |
239 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=1,swapped=1 | support | 1 | yes | CPU |
240 | CPU | GEGLU_QUICK | type=f32,ne_a=[128,2,2,2],v=1,split | support | 1 | yes | CPU |
241 | CPU | GEGLU_QUICK | type=f32,ne_a=[5,7,11,13],v=1,split | support | 1 | yes | CPU |
242 | CPU | GET_ROWS | type=f32,n=1,m=8,r=2,b=1,v=0 | support | 1 | yes | CPU |
243 | CPU | GET_ROWS | type=f32,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
244 | CPU | GET_ROWS | type=f32,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
245 | CPU | GET_ROWS | type=f32,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
246 | CPU | GET_ROWS | type=f32,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
247 | CPU | GET_ROWS | type=f16,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
248 | CPU | GET_ROWS | type=f16,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
249 | CPU | GET_ROWS | type=f16,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
250 | CPU | GET_ROWS | type=f16,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
251 | CPU | GET_ROWS | type=bf16,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
252 | CPU | GET_ROWS | type=bf16,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
253 | CPU | GET_ROWS | type=bf16,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
254 | CPU | GET_ROWS | type=bf16,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
255 | CPU | GET_ROWS | type=q4_0,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
256 | CPU | GET_ROWS | type=q4_0,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
257 | CPU | GET_ROWS | type=q4_0,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
258 | CPU | GET_ROWS | type=q4_0,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
259 | CPU | GET_ROWS | type=q4_1,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
260 | CPU | GET_ROWS | type=q4_1,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
261 | CPU | GET_ROWS | type=q4_1,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
262 | CPU | GET_ROWS | type=q4_1,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
263 | CPU | GET_ROWS | type=q5_0,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
264 | CPU | GET_ROWS | type=q5_0,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
265 | CPU | GET_ROWS | type=q5_0,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
266 | CPU | GET_ROWS | type=q5_0,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
267 | CPU | GET_ROWS | type=q5_1,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
268 | CPU | GET_ROWS | type=q5_1,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
269 | CPU | GET_ROWS | type=q5_1,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
270 | CPU | GET_ROWS | type=q5_1,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
271 | CPU | GET_ROWS | type=q8_0,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
272 | CPU | GET_ROWS | type=q8_0,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
273 | CPU | GET_ROWS | type=q8_0,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
274 | CPU | GET_ROWS | type=q8_0,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
275 | CPU | GET_ROWS | type=q2_K,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
276 | CPU | GET_ROWS | type=q2_K,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
277 | CPU | GET_ROWS | type=q2_K,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
278 | CPU | GET_ROWS | type=q2_K,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
279 | CPU | GET_ROWS | type=q3_K,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
280 | CPU | GET_ROWS | type=q3_K,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
281 | CPU | GET_ROWS | type=q3_K,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
282 | CPU | GET_ROWS | type=q3_K,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
283 | CPU | GET_ROWS | type=q4_K,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
284 | CPU | GET_ROWS | type=q4_K,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
285 | CPU | GET_ROWS | type=q4_K,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
286 | CPU | GET_ROWS | type=q4_K,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
287 | CPU | GET_ROWS | type=q5_K,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
288 | CPU | GET_ROWS | type=q5_K,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
289 | CPU | GET_ROWS | type=q5_K,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
290 | CPU | GET_ROWS | type=q5_K,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
291 | CPU | GET_ROWS | type=q6_K,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
292 | CPU | GET_ROWS | type=q6_K,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
293 | CPU | GET_ROWS | type=q6_K,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
294 | CPU | GET_ROWS | type=q6_K,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
295 | CPU | GET_ROWS | type=iq2_xxs,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
296 | CPU | GET_ROWS | type=iq2_xxs,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
297 | CPU | GET_ROWS | type=iq2_xxs,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
298 | CPU | GET_ROWS | type=iq2_xxs,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
299 | CPU | GET_ROWS | type=iq2_xs,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
300 | CPU | GET_ROWS | type=iq2_xs,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
301 | CPU | GET_ROWS | type=iq2_xs,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
302 | CPU | GET_ROWS | type=iq2_xs,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
303 | CPU | GET_ROWS | type=iq2_s,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
304 | CPU | GET_ROWS | type=iq2_s,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
305 | CPU | GET_ROWS | type=iq2_s,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
306 | CPU | GET_ROWS | type=iq2_s,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
307 | CPU | GET_ROWS | type=iq3_xxs,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
308 | CPU | GET_ROWS | type=iq3_xxs,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
309 | CPU | GET_ROWS | type=iq3_xxs,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
310 | CPU | GET_ROWS | type=iq3_xxs,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
311 | CPU | GET_ROWS | type=iq1_s,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
312 | CPU | GET_ROWS | type=iq1_s,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
313 | CPU | GET_ROWS | type=iq1_s,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
314 | CPU | GET_ROWS | type=iq1_s,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
315 | CPU | GET_ROWS | type=iq1_m,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
316 | CPU | GET_ROWS | type=iq1_m,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
317 | CPU | GET_ROWS | type=iq1_m,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
318 | CPU | GET_ROWS | type=iq1_m,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
319 | CPU | GET_ROWS | type=iq4_nl,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
320 | CPU | GET_ROWS | type=iq4_nl,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
321 | CPU | GET_ROWS | type=iq4_nl,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
322 | CPU | GET_ROWS | type=iq4_nl,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
323 | CPU | GET_ROWS | type=iq3_s,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
324 | CPU | GET_ROWS | type=iq3_s,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
325 | CPU | GET_ROWS | type=iq3_s,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
326 | CPU | GET_ROWS | type=iq3_s,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
327 | CPU | GET_ROWS | type=iq4_xs,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
328 | CPU | GET_ROWS | type=iq4_xs,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
329 | CPU | GET_ROWS | type=iq4_xs,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
330 | CPU | GET_ROWS | type=iq4_xs,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
331 | CPU | GET_ROWS | type=i32,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
332 | CPU | GET_ROWS | type=i32,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
333 | CPU | GET_ROWS | type=i32,n=256,m=5,r=4,b=7,v=0 | support | 1 | yes | CPU |
334 | CPU | GET_ROWS | type=i32,n=256,m=5,r=4,b=7,v=1 | support | 1 | yes | CPU |
335 | CPU | GET_ROWS_BACK | type=f32,n=1,m=8,r=2,b=1,v=0 | support | 1 | yes | CPU |
336 | CPU | GET_ROWS_BACK | type=f32,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
337 | CPU | GET_ROWS_BACK | type=f32,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
338 | CPU | GET_ROWS_BACK | type=f16,n=256,m=5,r=4,b=1,v=0 | support | 1 | yes | CPU |
339 | CPU | GET_ROWS_BACK | type=f16,n=256,m=5,r=4,b=1,v=1 | support | 1 | yes | CPU |
340 | CPU | GET_ROWS_BACK | type=bf16,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
341 | CPU | GET_ROWS_BACK | type=bf16,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
342 | CPU | GET_ROWS_BACK | type=q4_0,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
343 | CPU | GET_ROWS_BACK | type=q4_0,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
344 | CPU | GET_ROWS_BACK | type=q4_1,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
345 | CPU | GET_ROWS_BACK | type=q4_1,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
346 | CPU | GET_ROWS_BACK | type=q5_0,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
347 | CPU | GET_ROWS_BACK | type=q5_0,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
348 | CPU | GET_ROWS_BACK | type=q5_1,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
349 | CPU | GET_ROWS_BACK | type=q5_1,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
350 | CPU | GET_ROWS_BACK | type=q8_0,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
351 | CPU | GET_ROWS_BACK | type=q8_0,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
352 | CPU | GET_ROWS_BACK | type=q2_K,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
353 | CPU | GET_ROWS_BACK | type=q2_K,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
354 | CPU | GET_ROWS_BACK | type=q3_K,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
355 | CPU | GET_ROWS_BACK | type=q3_K,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
356 | CPU | GET_ROWS_BACK | type=q4_K,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
357 | CPU | GET_ROWS_BACK | type=q4_K,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
358 | CPU | GET_ROWS_BACK | type=q5_K,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
359 | CPU | GET_ROWS_BACK | type=q5_K,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
360 | CPU | GET_ROWS_BACK | type=q6_K,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
361 | CPU | GET_ROWS_BACK | type=q6_K,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
362 | CPU | GET_ROWS_BACK | type=iq2_xxs,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
363 | CPU | GET_ROWS_BACK | type=iq2_xxs,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
364 | CPU | GET_ROWS_BACK | type=iq2_xs,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
365 | CPU | GET_ROWS_BACK | type=iq2_xs,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
366 | CPU | GET_ROWS_BACK | type=iq2_s,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
367 | CPU | GET_ROWS_BACK | type=iq2_s,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
368 | CPU | GET_ROWS_BACK | type=iq3_xxs,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
369 | CPU | GET_ROWS_BACK | type=iq3_xxs,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
370 | CPU | GET_ROWS_BACK | type=iq1_s,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
371 | CPU | GET_ROWS_BACK | type=iq1_s,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
372 | CPU | GET_ROWS_BACK | type=iq1_m,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
373 | CPU | GET_ROWS_BACK | type=iq1_m,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
374 | CPU | GET_ROWS_BACK | type=iq4_nl,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
375 | CPU | GET_ROWS_BACK | type=iq4_nl,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
376 | CPU | GET_ROWS_BACK | type=iq3_s,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
377 | CPU | GET_ROWS_BACK | type=iq3_s,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
378 | CPU | GET_ROWS_BACK | type=iq4_xs,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
379 | CPU | GET_ROWS_BACK | type=iq4_xs,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
380 | CPU | GET_ROWS_BACK | type=i32,n=256,m=5,r=4,b=1,v=0 | support | 0 | no | CPU |
381 | CPU | GET_ROWS_BACK | type=i32,n=256,m=5,r=4,b=1,v=1 | support | 0 | no | CPU |
382 | CPU | SET_ROWS | type=f32,ne=[1,8,1,3],nr23=[1,1],r=2,v=0 | support | 1 | yes | CPU |
383 | CPU | SET_ROWS | type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
384 | CPU | SET_ROWS | type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
385 | CPU | SET_ROWS | type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
386 | CPU | SET_ROWS | type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
387 | CPU | SET_ROWS | type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
388 | CPU | SET_ROWS | type=f32,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
389 | CPU | SET_ROWS | type=f32,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
390 | CPU | SET_ROWS | type=f32,ne=[3,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
391 | CPU | SET_ROWS | type=f32,ne=[31,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
392 | CPU | SET_ROWS | type=f32,ne=[33,5,1,1],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
393 | CPU | SET_ROWS | type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
394 | CPU | SET_ROWS | type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
395 | CPU | SET_ROWS | type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
396 | CPU | SET_ROWS | type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
397 | CPU | SET_ROWS | type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
398 | CPU | SET_ROWS | type=f32,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
399 | CPU | SET_ROWS | type=f32,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
400 | CPU | SET_ROWS | type=f32,ne=[3,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
401 | CPU | SET_ROWS | type=f32,ne=[31,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
402 | CPU | SET_ROWS | type=f32,ne=[33,5,1,7],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
403 | CPU | SET_ROWS | type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
404 | CPU | SET_ROWS | type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
405 | CPU | SET_ROWS | type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
406 | CPU | SET_ROWS | type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
407 | CPU | SET_ROWS | type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
408 | CPU | SET_ROWS | type=f16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
409 | CPU | SET_ROWS | type=f16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
410 | CPU | SET_ROWS | type=f16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
411 | CPU | SET_ROWS | type=f16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
412 | CPU | SET_ROWS | type=f16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
413 | CPU | SET_ROWS | type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
414 | CPU | SET_ROWS | type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
415 | CPU | SET_ROWS | type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
416 | CPU | SET_ROWS | type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
417 | CPU | SET_ROWS | type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
418 | CPU | SET_ROWS | type=f16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
419 | CPU | SET_ROWS | type=f16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
420 | CPU | SET_ROWS | type=f16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
421 | CPU | SET_ROWS | type=f16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
422 | CPU | SET_ROWS | type=f16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
423 | CPU | SET_ROWS | type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
424 | CPU | SET_ROWS | type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
425 | CPU | SET_ROWS | type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
426 | CPU | SET_ROWS | type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
427 | CPU | SET_ROWS | type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
428 | CPU | SET_ROWS | type=bf16,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
429 | CPU | SET_ROWS | type=bf16,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
430 | CPU | SET_ROWS | type=bf16,ne=[3,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
431 | CPU | SET_ROWS | type=bf16,ne=[31,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
432 | CPU | SET_ROWS | type=bf16,ne=[33,5,1,1],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
433 | CPU | SET_ROWS | type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
434 | CPU | SET_ROWS | type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
435 | CPU | SET_ROWS | type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
436 | CPU | SET_ROWS | type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
437 | CPU | SET_ROWS | type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=0 | support | 1 | yes | CPU |
438 | CPU | SET_ROWS | type=bf16,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
439 | CPU | SET_ROWS | type=bf16,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
440 | CPU | SET_ROWS | type=bf16,ne=[3,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
441 | CPU | SET_ROWS | type=bf16,ne=[31,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
442 | CPU | SET_ROWS | type=bf16,ne=[33,5,1,7],nr23=[2,3],r=1,v=1 | support | 1 | yes | CPU |
443 | CPU | SET_ROWS | type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
444 | CPU | SET_ROWS | type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
445 | CPU | SET_ROWS | type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
446 | CPU | SET_ROWS | type=q4_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
447 | CPU | SET_ROWS | type=q4_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
448 | CPU | SET_ROWS | type=q4_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
449 | CPU | SET_ROWS | type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
450 | CPU | SET_ROWS | type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
451 | CPU | SET_ROWS | type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
452 | CPU | SET_ROWS | type=q4_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
453 | CPU | SET_ROWS | type=q4_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
454 | CPU | SET_ROWS | type=q4_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
455 | CPU | SET_ROWS | type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
456 | CPU | SET_ROWS | type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
457 | CPU | SET_ROWS | type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
458 | CPU | SET_ROWS | type=q4_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
459 | CPU | SET_ROWS | type=q4_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
460 | CPU | SET_ROWS | type=q4_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
461 | CPU | SET_ROWS | type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
462 | CPU | SET_ROWS | type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
463 | CPU | SET_ROWS | type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
464 | CPU | SET_ROWS | type=q4_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
465 | CPU | SET_ROWS | type=q4_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
466 | CPU | SET_ROWS | type=q4_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
467 | CPU | SET_ROWS | type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
468 | CPU | SET_ROWS | type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
469 | CPU | SET_ROWS | type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
470 | CPU | SET_ROWS | type=q5_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
471 | CPU | SET_ROWS | type=q5_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
472 | CPU | SET_ROWS | type=q5_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
473 | CPU | SET_ROWS | type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
474 | CPU | SET_ROWS | type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
475 | CPU | SET_ROWS | type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
476 | CPU | SET_ROWS | type=q5_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
477 | CPU | SET_ROWS | type=q5_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
478 | CPU | SET_ROWS | type=q5_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
479 | CPU | SET_ROWS | type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
480 | CPU | SET_ROWS | type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
481 | CPU | SET_ROWS | type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
482 | CPU | SET_ROWS | type=q5_1,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
483 | CPU | SET_ROWS | type=q5_1,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
484 | CPU | SET_ROWS | type=q5_1,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
485 | CPU | SET_ROWS | type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
486 | CPU | SET_ROWS | type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
487 | CPU | SET_ROWS | type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
488 | CPU | SET_ROWS | type=q5_1,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
489 | CPU | SET_ROWS | type=q5_1,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
490 | CPU | SET_ROWS | type=q5_1,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
491 | CPU | SET_ROWS | type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
492 | CPU | SET_ROWS | type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
493 | CPU | SET_ROWS | type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
494 | CPU | SET_ROWS | type=q8_0,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
495 | CPU | SET_ROWS | type=q8_0,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
496 | CPU | SET_ROWS | type=q8_0,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
497 | CPU | SET_ROWS | type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
498 | CPU | SET_ROWS | type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
499 | CPU | SET_ROWS | type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
500 | CPU | SET_ROWS | type=q8_0,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
501 | CPU | SET_ROWS | type=q8_0,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
502 | CPU | SET_ROWS | type=q8_0,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
503 | CPU | SET_ROWS | type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
504 | CPU | SET_ROWS | type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
505 | CPU | SET_ROWS | type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
506 | CPU | SET_ROWS | type=q2_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
507 | CPU | SET_ROWS | type=q2_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
508 | CPU | SET_ROWS | type=q2_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
509 | CPU | SET_ROWS | type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
510 | CPU | SET_ROWS | type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
511 | CPU | SET_ROWS | type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
512 | CPU | SET_ROWS | type=q2_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
513 | CPU | SET_ROWS | type=q2_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
514 | CPU | SET_ROWS | type=q2_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
515 | CPU | SET_ROWS | type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
516 | CPU | SET_ROWS | type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
517 | CPU | SET_ROWS | type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
518 | CPU | SET_ROWS | type=q3_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
519 | CPU | SET_ROWS | type=q3_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
520 | CPU | SET_ROWS | type=q3_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
521 | CPU | SET_ROWS | type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
522 | CPU | SET_ROWS | type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
523 | CPU | SET_ROWS | type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
524 | CPU | SET_ROWS | type=q3_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
525 | CPU | SET_ROWS | type=q3_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
526 | CPU | SET_ROWS | type=q3_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
527 | CPU | SET_ROWS | type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
528 | CPU | SET_ROWS | type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
529 | CPU | SET_ROWS | type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
530 | CPU | SET_ROWS | type=q4_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
531 | CPU | SET_ROWS | type=q4_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
532 | CPU | SET_ROWS | type=q4_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
533 | CPU | SET_ROWS | type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
534 | CPU | SET_ROWS | type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
535 | CPU | SET_ROWS | type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
536 | CPU | SET_ROWS | type=q4_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
537 | CPU | SET_ROWS | type=q4_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
538 | CPU | SET_ROWS | type=q4_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
539 | CPU | SET_ROWS | type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
540 | CPU | SET_ROWS | type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
541 | CPU | SET_ROWS | type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
542 | CPU | SET_ROWS | type=q5_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
543 | CPU | SET_ROWS | type=q5_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
544 | CPU | SET_ROWS | type=q5_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
545 | CPU | SET_ROWS | type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
546 | CPU | SET_ROWS | type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
547 | CPU | SET_ROWS | type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
548 | CPU | SET_ROWS | type=q5_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
549 | CPU | SET_ROWS | type=q5_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
550 | CPU | SET_ROWS | type=q5_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
551 | CPU | SET_ROWS | type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
552 | CPU | SET_ROWS | type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
553 | CPU | SET_ROWS | type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
554 | CPU | SET_ROWS | type=q6_K,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
555 | CPU | SET_ROWS | type=q6_K,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
556 | CPU | SET_ROWS | type=q6_K,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
557 | CPU | SET_ROWS | type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
558 | CPU | SET_ROWS | type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
559 | CPU | SET_ROWS | type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
560 | CPU | SET_ROWS | type=q6_K,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
561 | CPU | SET_ROWS | type=q6_K,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
562 | CPU | SET_ROWS | type=q6_K,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
563 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
564 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
565 | CPU | SET_ROWS | type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
566 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
567 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
568 | CPU | SET_ROWS | type=iq2_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
569 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
570 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
571 | CPU | SET_ROWS | type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
572 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
573 | CPU | SET_ROWS | type=iq2_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
574 | CPU | SET_ROWS | type=iq2_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
575 | CPU | SET_ROWS | type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
576 | CPU | SET_ROWS | type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
577 | CPU | SET_ROWS | type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
578 | CPU | SET_ROWS | type=iq2_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
579 | CPU | SET_ROWS | type=iq2_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
580 | CPU | SET_ROWS | type=iq2_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
581 | CPU | SET_ROWS | type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
582 | CPU | SET_ROWS | type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
583 | CPU | SET_ROWS | type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
584 | CPU | SET_ROWS | type=iq2_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
585 | CPU | SET_ROWS | type=iq2_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
586 | CPU | SET_ROWS | type=iq2_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
587 | CPU | SET_ROWS | type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
588 | CPU | SET_ROWS | type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
589 | CPU | SET_ROWS | type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
590 | CPU | SET_ROWS | type=iq2_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
591 | CPU | SET_ROWS | type=iq2_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
592 | CPU | SET_ROWS | type=iq2_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
593 | CPU | SET_ROWS | type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
594 | CPU | SET_ROWS | type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
595 | CPU | SET_ROWS | type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
596 | CPU | SET_ROWS | type=iq2_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
597 | CPU | SET_ROWS | type=iq2_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
598 | CPU | SET_ROWS | type=iq2_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
599 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
600 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
601 | CPU | SET_ROWS | type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
602 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
603 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
604 | CPU | SET_ROWS | type=iq3_xxs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
605 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
606 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
607 | CPU | SET_ROWS | type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
608 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
609 | CPU | SET_ROWS | type=iq3_xxs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
610 | CPU | SET_ROWS | type=iq3_xxs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
611 | CPU | SET_ROWS | type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
612 | CPU | SET_ROWS | type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
613 | CPU | SET_ROWS | type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
614 | CPU | SET_ROWS | type=iq1_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
615 | CPU | SET_ROWS | type=iq1_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
616 | CPU | SET_ROWS | type=iq1_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
617 | CPU | SET_ROWS | type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
618 | CPU | SET_ROWS | type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
619 | CPU | SET_ROWS | type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
620 | CPU | SET_ROWS | type=iq1_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
621 | CPU | SET_ROWS | type=iq1_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
622 | CPU | SET_ROWS | type=iq1_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
623 | CPU | SET_ROWS | type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
624 | CPU | SET_ROWS | type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
625 | CPU | SET_ROWS | type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
626 | CPU | SET_ROWS | type=iq1_m,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
627 | CPU | SET_ROWS | type=iq1_m,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
628 | CPU | SET_ROWS | type=iq1_m,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
629 | CPU | SET_ROWS | type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
630 | CPU | SET_ROWS | type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
631 | CPU | SET_ROWS | type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
632 | CPU | SET_ROWS | type=iq1_m,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
633 | CPU | SET_ROWS | type=iq1_m,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
634 | CPU | SET_ROWS | type=iq1_m,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
635 | CPU | SET_ROWS | type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
636 | CPU | SET_ROWS | type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
637 | CPU | SET_ROWS | type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
638 | CPU | SET_ROWS | type=iq4_nl,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
639 | CPU | SET_ROWS | type=iq4_nl,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
640 | CPU | SET_ROWS | type=iq4_nl,ne=[96,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
641 | CPU | SET_ROWS | type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
642 | CPU | SET_ROWS | type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
643 | CPU | SET_ROWS | type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
644 | CPU | SET_ROWS | type=iq4_nl,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
645 | CPU | SET_ROWS | type=iq4_nl,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
646 | CPU | SET_ROWS | type=iq4_nl,ne=[96,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
647 | CPU | SET_ROWS | type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
648 | CPU | SET_ROWS | type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
649 | CPU | SET_ROWS | type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
650 | CPU | SET_ROWS | type=iq3_s,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
651 | CPU | SET_ROWS | type=iq3_s,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
652 | CPU | SET_ROWS | type=iq3_s,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
653 | CPU | SET_ROWS | type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 0 | no | CPU |
654 | CPU | SET_ROWS | type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 0 | no | CPU |
655 | CPU | SET_ROWS | type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 0 | no | CPU |
656 | CPU | SET_ROWS | type=iq3_s,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 0 | no | CPU |
657 | CPU | SET_ROWS | type=iq3_s,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 0 | no | CPU |
658 | CPU | SET_ROWS | type=iq3_s,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 0 | no | CPU |
659 | CPU | SET_ROWS | type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
660 | CPU | SET_ROWS | type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
661 | CPU | SET_ROWS | type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
662 | CPU | SET_ROWS | type=iq4_xs,ne=[256,5,1,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
663 | CPU | SET_ROWS | type=iq4_xs,ne=[256,11,1,1],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
664 | CPU | SET_ROWS | type=iq4_xs,ne=[768,3,1,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
665 | CPU | SET_ROWS | type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=0 | support | 1 | yes | CPU |
666 | CPU | SET_ROWS | type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=0 | support | 1 | yes | CPU |
667 | CPU | SET_ROWS | type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=0 | support | 1 | yes | CPU |
668 | CPU | SET_ROWS | type=iq4_xs,ne=[256,5,7,3],nr23=[1,1],r=1,v=1 | support | 1 | yes | CPU |
669 | CPU | SET_ROWS | type=iq4_xs,ne=[256,11,1,7],nr23=[2,3],r=7,v=1 | support | 1 | yes | CPU |
670 | CPU | SET_ROWS | type=iq4_xs,ne=[768,3,7,1],nr23=[2,3],r=2,v=1 | support | 1 | yes | CPU |
671 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
672 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
673 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
674 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
675 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
676 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
677 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
678 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
679 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
680 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
681 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
682 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
683 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
684 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
685 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
686 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
687 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
688 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
689 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
690 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
691 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
692 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
693 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
694 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
695 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
696 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
697 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
698 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
699 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
700 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
701 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
702 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
703 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
704 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
705 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
706 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
707 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
708 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
709 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
710 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
711 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
712 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
713 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
714 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
715 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
716 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
717 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
718 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
719 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
720 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
721 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
722 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
723 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
724 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
725 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
726 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
727 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
728 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
729 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
730 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
731 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
732 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
733 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
734 | CPU | POOL_2D | pool_type=avg,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
735 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
736 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
737 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
738 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
739 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
740 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
741 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
742 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
743 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
744 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
745 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
746 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
747 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
748 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
749 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
750 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=1,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
751 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
752 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
753 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
754 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
755 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
756 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
757 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
758 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
759 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
760 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
761 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
762 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
763 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
764 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
765 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
766 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=1,k1=3,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
767 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
768 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
769 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
770 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
771 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
772 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
773 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
774 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
775 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
776 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
777 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
778 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
779 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
780 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
781 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
782 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=1,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
783 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
784 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
785 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
786 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
787 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
788 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
789 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
790 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=1,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
791 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=0 | support | 1 | yes | CPU |
792 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=0,p1=1 | support | 1 | yes | CPU |
793 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=0 | support | 1 | yes | CPU |
794 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=1,p0=1,p1=1 | support | 1 | yes | CPU |
795 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=0 | support | 1 | yes | CPU |
796 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=0,p1=1 | support | 1 | yes | CPU |
797 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=0 | support | 1 | yes | CPU |
798 | CPU | POOL_2D | pool_type=max,type_input=f32,ne_input=[10,10,3,1],k0=3,k1=3,s0=2,s1=2,p0=1,p1=1 | support | 1 | yes | CPU |
799 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
800 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
801 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[3000,128,1,1],ne_kernel=[3,128,1280,1],s0=1,s1=0,p0=1,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
802 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
803 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0 | support | 1 | yes | CPU |
804 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
805 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=1,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0 | support | 1 | yes | CPU |
806 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
807 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=0,p1=0,d0=3,d1=0,is_2D=0 | support | 1 | yes | CPU |
808 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=1,d1=0,is_2D=0 | support | 1 | yes | CPU |
809 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,2,2,1],ne_kernel=[3,2,2,1],s0=3,s1=0,p0=3,p1=0,d0=3,d1=0,is_2D=0 | support | 1 | yes | CPU |
810 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
811 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f32,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
812 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[10,10,3,1],ne_kernel=[3,3,3,1],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
813 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
814 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
815 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
816 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
817 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
818 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
819 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
820 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
821 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
822 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
823 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
824 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
825 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
826 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
827 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
828 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
829 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
830 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
831 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
832 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
833 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
834 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
835 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
836 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
837 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
838 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
839 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
840 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
841 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
842 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
843 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
844 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=1,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
845 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
846 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
847 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
848 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
849 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
850 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
851 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
852 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=0,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
853 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
854 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
855 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
856 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
857 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
858 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
859 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
860 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=1,p0=3,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
861 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
862 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
863 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
864 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
865 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
866 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
867 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
868 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=0,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
869 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
870 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
871 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
872 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=0,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
873 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
874 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=1,d1=3,is_2D=1 | support | 1 | yes | CPU |
875 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=1,is_2D=1 | support | 1 | yes | CPU |
876 | CPU | IM2COL | type_input=f32,type_kernel=f32,dst_type=f32,ne_input=[20,20,2,2],ne_kernel=[3,3,2,2],s0=3,s1=3,p0=3,p1=3,d0=3,d1=3,is_2D=1 | support | 1 | yes | CPU |
877 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,32],ne_kernel=[3,3,1,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
878 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,32],ne_kernel=[3,3,2,32],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
879 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,1024],ne_kernel=[3,3,1,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
880 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,1024],ne_kernel=[3,3,2,1024],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
881 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2048],ne_kernel=[3,3,1,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
882 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2048],ne_kernel=[3,3,2,2048],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
883 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,1,2560],ne_kernel=[3,3,1,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
884 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[12,12,2,2560],ne_kernel=[3,3,2,2560],s0=1,s1=1,p0=1,p1=1,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
885 | CPU | IM2COL | type_input=f32,type_kernel=f16,dst_type=f16,ne_input=[5,5,1,32],ne_kernel=[3,4,1,32],s0=1,s1=1,p0=0,p1=0,d0=1,d1=1,is_2D=1 | support | 1 | yes | CPU |
886 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
887 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
888 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
889 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
890 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
891 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
892 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
893 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
894 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
895 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
896 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
897 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
898 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
899 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
900 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
901 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
902 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
903 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
904 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
905 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
906 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
907 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
908 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
909 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
910 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
911 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
912 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
913 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
914 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
915 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
916 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
917 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
918 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
919 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
920 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
921 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
922 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
923 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
924 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
925 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
926 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
927 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
928 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
929 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
930 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
931 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
932 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
933 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
934 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
935 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
936 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
937 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
938 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
939 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
940 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
941 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
942 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
943 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
944 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
945 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
946 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
947 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
948 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
949 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
950 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
951 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
952 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
953 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
954 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
955 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
956 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
957 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
958 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
959 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
960 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
961 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
962 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
963 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
964 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
965 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
966 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
967 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
968 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
969 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
970 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
971 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
972 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
973 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
974 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
975 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
976 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
977 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
978 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
979 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
980 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
981 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
982 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
983 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
984 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
985 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
986 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
987 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
988 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
989 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
990 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
991 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
992 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
993 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
994 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
995 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
996 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
997 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
998 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
999 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1000 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1001 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1002 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1003 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1004 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1005 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1006 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1007 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1008 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1009 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1010 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1011 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1012 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1013 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1014 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1015 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1016 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1017 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1018 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1019 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1020 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1021 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1022 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1023 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1024 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1025 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1026 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1027 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1028 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1029 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1030 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1031 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1032 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1033 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1034 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1035 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1036 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1037 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1038 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1039 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1040 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1041 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1042 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1043 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1044 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1045 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1046 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1047 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1048 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1049 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1050 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1051 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1052 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1053 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1054 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1055 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1056 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1057 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1058 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1059 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1060 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1061 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1062 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1063 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1064 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1065 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1066 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1067 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1068 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1069 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1070 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1071 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1072 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1073 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1074 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1075 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1076 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1077 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1078 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1079 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1080 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1081 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=1,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1082 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1083 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1084 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1085 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1086 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1087 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1088 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1089 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1090 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1091 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1092 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1093 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1094 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1095 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1096 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1097 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1098 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1099 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1100 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1101 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1102 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1103 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1104 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1105 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1106 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1107 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1108 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1109 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1110 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1111 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1112 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1113 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1114 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1115 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1116 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1117 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1118 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1119 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1120 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1121 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1122 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1123 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1124 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1125 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1126 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1127 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1128 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1129 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1130 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1131 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1132 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1133 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1134 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1135 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1136 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1137 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1138 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1139 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1140 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1141 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1142 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1143 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1144 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1145 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1146 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1147 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1148 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1149 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1150 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1151 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1152 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1153 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1154 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1155 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1156 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1157 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1158 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1159 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1160 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1161 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1162 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1163 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1164 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1165 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1166 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1167 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1168 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1169 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1170 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1171 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1172 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1173 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1174 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1175 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1176 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1177 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1178 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1179 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1180 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1181 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1182 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1183 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1184 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1185 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1186 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1187 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1188 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1189 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1190 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1191 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1192 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1193 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1194 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1195 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1196 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1197 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1198 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1199 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1200 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1201 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1202 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1203 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1204 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1205 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1206 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1207 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1208 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1209 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1210 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1211 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1212 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1213 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1214 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1215 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1216 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1217 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1218 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1219 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1220 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1221 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1222 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1223 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1224 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1225 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1226 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1227 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1228 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1229 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1230 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1231 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1232 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1233 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1234 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1235 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1236 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1237 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1238 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1239 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1240 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1241 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1242 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1243 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1244 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1245 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1246 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1247 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1248 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1249 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1250 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1251 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1252 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1253 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1254 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1255 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1256 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1257 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1258 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1259 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1260 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1261 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1262 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1263 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1264 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1265 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1266 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1267 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1268 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1269 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1270 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1271 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1272 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1273 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1274 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1275 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1276 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1277 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=1,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1278 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1279 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1280 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1281 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1282 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1283 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1284 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1285 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1286 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1287 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1288 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1289 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1290 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1291 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1292 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1293 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1294 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1295 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1296 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1297 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1298 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1299 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1300 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1301 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1302 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1303 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1304 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1305 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1306 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1307 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1308 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1309 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1310 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1311 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1312 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1313 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1314 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1315 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1316 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1317 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1318 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1319 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1320 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1321 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1322 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1323 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1324 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1325 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1326 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1327 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1328 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1329 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1330 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1331 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1332 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1333 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1334 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1335 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1336 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1337 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1338 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1339 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1340 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1341 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1342 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1343 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1344 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1345 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1346 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1347 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1348 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1349 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1350 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1351 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1352 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1353 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1354 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1355 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1356 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1357 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1358 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1359 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1360 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1361 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1362 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1363 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1364 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1365 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1366 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1367 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1368 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1369 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1370 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1371 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1372 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1373 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1374 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1375 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1376 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1377 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1378 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1379 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1380 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1381 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1382 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1383 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1384 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1385 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1386 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1387 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1388 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1389 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1390 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1391 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1392 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1393 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1394 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1395 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1396 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1397 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1398 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1399 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1400 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1401 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1402 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1403 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1404 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1405 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1406 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1407 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1408 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1409 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1410 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1411 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1412 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1413 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1414 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1415 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1416 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1417 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1418 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1419 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1420 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1421 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1422 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1423 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1424 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1425 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1426 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1427 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1428 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1429 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1430 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1431 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1432 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1433 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1434 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1435 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1436 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1437 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1438 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1439 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1440 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1441 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1442 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1443 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1444 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1445 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1446 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1447 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1448 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1449 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1450 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1451 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1452 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1453 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1454 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1455 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1456 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1457 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1458 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1459 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1460 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1461 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1462 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1463 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1464 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1465 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1466 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1467 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1468 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1469 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1470 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1471 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1472 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1473 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=3,stride1=5,padding0=5,padding1=2,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1474 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1475 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1476 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1477 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1478 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1479 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1480 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1481 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1482 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1483 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1484 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1485 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1486 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1487 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1488 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1489 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1490 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1491 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1492 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1493 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1494 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1495 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1496 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1497 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1498 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1499 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1500 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1501 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1502 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1503 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1504 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1505 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1506 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1507 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1508 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1509 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1510 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1511 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1512 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1513 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1514 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1515 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1516 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1517 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1518 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1519 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1520 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1521 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1522 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1523 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1524 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1525 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1526 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1527 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1528 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1529 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1530 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1531 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1532 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1533 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1534 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1535 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1536 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,1,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1537 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1538 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1539 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1540 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1541 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1542 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1543 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1544 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1545 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1546 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1547 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1548 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1549 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1550 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,2,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1551 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1552 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1553 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1554 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1555 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1556 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1557 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1558 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1559 | CPU | CONV_2D | ne_input=[1,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1560 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1561 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1562 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1563 | CPU | CONV_2D | ne_input=[141,1,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1564 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,3,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1565 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1566 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[1,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1567 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1568 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[2,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1569 | CPU | CONV_2D | ne_input=[1,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1570 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[3,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1571 | CPU | CONV_2D | ne_input=[141,133,1,2],ne_kernel=[11,11,1,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1572 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1573 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1574 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1575 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1576 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1577 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1578 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1579 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1580 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1581 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1582 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1583 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1584 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1585 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1586 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1587 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1588 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1589 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1590 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1591 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1592 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1593 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1594 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1595 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1596 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1597 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1598 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1599 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1600 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1601 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1602 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1603 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1604 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1605 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1606 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1607 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1608 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1609 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1610 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1611 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1612 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1613 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1614 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1615 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1616 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1617 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1618 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1619 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1620 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,1],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1621 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1622 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1623 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1624 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1625 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1626 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1627 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1628 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1629 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1630 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1631 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1632 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1633 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1634 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,1,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1635 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1636 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1637 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1638 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1639 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1640 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1641 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1642 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1643 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1644 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1645 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1646 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1647 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1648 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,2,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1649 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1650 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1651 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1652 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1653 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1654 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1655 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1656 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1657 | CPU | CONV_2D | ne_input=[1,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1658 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1659 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1660 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1661 | CPU | CONV_2D | ne_input=[141,1,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1662 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,3,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1663 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1664 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[1,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1665 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1666 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[2,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1667 | CPU | CONV_2D | ne_input=[1,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1668 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[3,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1669 | CPU | CONV_2D | ne_input=[141,133,25,2],ne_kernel=[11,11,25,12],stride0=3,stride1=5,padding0=5,padding1=5,dilation0=2,dilation1=4,cwhn=0 | support | 1 | yes | CPU |
1670 | CPU | CONV_2D_DW | ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=0 | support | 1 | yes | CPU |
1671 | CPU | CONV_2D_DW | ne_input=[17,34,9,1],ne_kernel=[3,3,1,9],stride=1,padding=0,dilation=1,cwhn=1 | support | 1 | yes | CPU |
1672 | CPU | CONV_2D_DW | ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=0 | support | 1 | yes | CPU |
1673 | CPU | CONV_2D_DW | ne_input=[32,8,64,1],ne_kernel=[3,3,1,64],stride=2,padding=1,dilation=1,cwhn=1 | support | 1 | yes | CPU |
1674 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1675 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1676 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1677 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1678 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1679 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1680 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1681 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1682 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1683 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1684 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1685 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1686 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1687 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1688 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1689 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1690 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1691 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1692 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1693 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1694 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1695 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1696 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1697 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1698 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1699 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1700 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,1,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1701 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1702 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1703 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1704 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1705 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1706 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1707 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1708 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1709 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1710 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1711 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1712 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1713 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1714 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1715 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1716 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1717 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1718 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1719 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1720 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1721 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1722 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1723 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1724 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1725 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1726 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1727 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,1,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1728 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1729 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1730 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1731 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1732 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1733 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1734 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1735 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1736 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1737 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1738 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1739 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1740 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1741 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1742 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1743 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1744 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1745 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[3,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1746 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1747 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1748 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1749 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1750 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1751 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1752 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1753 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1754 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,1,1,1],ne_kernel=[1337,9,1,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1755 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1756 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1757 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1758 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1759 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1760 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1761 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1762 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1763 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1764 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1765 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1766 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1767 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1768 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1769 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1770 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1771 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1772 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[3,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1773 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1774 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1775 | CPU | CONV_TRANSPOSE_1D | ne_input=[1,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1776 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1777 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1778 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1779 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1780 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1781 | CPU | CONV_TRANSPOSE_1D | ne_input=[13,7,1,1],ne_kernel=[1337,9,7,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1782 | CPU | CONV_TRANSPOSE_1D | ne_input=[197,32,1,1],ne_kernel=[16,32,32,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1783 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=3,p0=0,d0=1 | support | 1 | yes | CPU |
1784 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1785 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[2,3,2,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1786 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=2,p0=0,d0=1 | support | 1 | yes | CPU |
1787 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[3,2,2,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1788 | CPU | CONV_TRANSPOSE_1D | ne_input=[3,2,1,1],ne_kernel=[3,1,2,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1789 | CPU | CONV_TRANSPOSE_1D | ne_input=[2,1,1,1],ne_kernel=[3,1,1,1],s0=1,p0=0,d0=1 | support | 1 | yes | CPU |
1790 | CPU | CONV_TRANSPOSE_2D | ne_input=[3,2,3,1],ne_kernel=[2,2,1,3],stride=1 | support | 1 | yes | CPU |
1791 | CPU | CONV_TRANSPOSE_2D | ne_input=[10,10,9,1],ne_kernel=[3,3,1,9],stride=2 | support | 1 | yes | CPU |
1792 | CPU | COUNT_EQUAL | type=f32,ne=[4,500,1,1] | support | 1 | yes | CPU |
1793 | CPU | COUNT_EQUAL | type=f32,ne=[4,5000,1,1] | support | 1 | yes | CPU |
1794 | CPU | ARGMAX | type=f32,ne=[32,1,1,1] | support | 1 | yes | CPU |
1795 | CPU | ARGMAX | type=f32,ne=[100,10,1,1] | support | 1 | yes | CPU |
1796 | CPU | ARGMAX | type=f32,ne=[1024,10,1,1] | support | 1 | yes | CPU |
1797 | CPU | ARGMAX | type=f32,ne=[1024,12,1,1] | support | 1 | yes | CPU |
1798 | CPU | ARGMAX | type=f32,ne=[2000,10,1,1] | support | 1 | yes | CPU |
1799 | CPU | ARGMAX | type=f32,ne=[5438,3,1,1] | support | 1 | yes | CPU |
1800 | CPU | REPEAT | type=f32,ne=[10,5,4,1],nr=[1,1,1,1] | support | 1 | yes | CPU |
1801 | CPU | REPEAT | type=f32,ne=[10,5,4,1],nr=[2,1,1,1] | support | 1 | yes | CPU |
1802 | CPU | REPEAT | type=f32,ne=[10,5,4,1],nr=[1,2,1,1] | support | 1 | yes | CPU |
1803 | CPU | REPEAT | type=f32,ne=[10,5,4,1],nr=[1,1,2,1] | support | 1 | yes | CPU |
1804 | CPU | REPEAT | type=f32,ne=[10,5,4,1],nr=[1,1,1,2] | support | 1 | yes | CPU |
1805 | CPU | REPEAT | type=i32,ne=[10,5,4,1],nr=[2,1,1,1] | support | 1 | yes | CPU |
1806 | CPU | REPEAT | type=i16,ne=[10,5,4,1],nr=[1,1,1,2] | support | 1 | yes | CPU |
1807 | CPU | REPEAT | type=f32,ne=[10,5,4,3],nr=[1,1,1,1] | support | 1 | yes | CPU |
1808 | CPU | REPEAT | type=f32,ne=[10,5,4,3],nr=[2,1,1,1] | support | 1 | yes | CPU |
1809 | CPU | REPEAT | type=f32,ne=[10,5,4,3],nr=[1,2,1,1] | support | 1 | yes | CPU |
1810 | CPU | REPEAT | type=f32,ne=[10,5,4,3],nr=[1,1,2,1] | support | 1 | yes | CPU |
1811 | CPU | REPEAT | type=f32,ne=[10,5,4,3],nr=[1,1,1,2] | support | 1 | yes | CPU |
1812 | CPU | REPEAT | type=i32,ne=[10,5,4,3],nr=[2,1,1,1] | support | 1 | yes | CPU |
1813 | CPU | REPEAT | type=i16,ne=[10,5,4,3],nr=[1,1,1,2] | support | 1 | yes | CPU |
1814 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=0 | support | 1 | yes | CPU |
1815 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=0 | support | 1 | yes | CPU |
1816 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=0 | support | 1 | yes | CPU |
1817 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=0 | support | 1 | yes | CPU |
1818 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=0 | support | 1 | yes | CPU |
1819 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,1,1],v=1 | support | 1 | yes | CPU |
1820 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[2,1,1,1],v=1 | support | 1 | yes | CPU |
1821 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,2,1,1],v=1 | support | 1 | yes | CPU |
1822 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,2,1],v=1 | support | 1 | yes | CPU |
1823 | CPU | REPEAT_BACK | type=f32,ne=[8,6,4,2],nr=[1,1,1,2],v=1 | support | 1 | yes | CPU |
1824 | CPU | DUP | type=f32,ne=[10,10,20,1] | support | 1 | yes | CPU |
1825 | CPU | DUP | type=f16,ne=[10,10,20,1] | support | 1 | yes | CPU |
1826 | CPU | DUP | type=i32,ne=[10,10,20,1] | support | 1 | yes | CPU |
1827 | CPU | DUP | type=i16,ne=[10,10,20,1] | support | 1 | yes | CPU |
1828 | CPU | DUP | type=f32,ne=[10,10,5,1],permute=[0,2,1,3] | support | 1 | yes | CPU |
1829 | CPU | DUP | type=f16,ne=[10,10,5,1],permute=[0,2,1,3] | support | 1 | yes | CPU |
1830 | CPU | DUP | type=f32,ne=[10,10,5,1],permute=[1,0,2,3] | support | 1 | yes | CPU |
1831 | CPU | DUP | type=f16,ne=[10,10,5,1],permute=[1,0,2,3] | support | 1 | yes | CPU |
1832 | CPU | DUP | type=i16,ne=[10,8,3,1],permute=[0,2,1,3] | support | 1 | yes | CPU |
1833 | CPU | DUP | type=i16,ne=[10,8,3,1],permute=[1,2,0,3] | support | 1 | yes | CPU |
1834 | CPU | SET | type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=1 | support | 1 | yes | CPU |
1835 | CPU | SET | type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=2 | support | 1 | yes | CPU |
1836 | CPU | SET | type_src=f32,type_dst=f32,ne=[6,5,4,3],dim=3 | support | 1 | yes | CPU |
1837 | CPU | SET | type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=1 | support | 1 | yes | CPU |
1838 | CPU | SET | type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=2 | support | 1 | yes | CPU |
1839 | CPU | SET | type_src=i32,type_dst=i32,ne=[6,5,4,3],dim=3 | support | 1 | yes | CPU |
1840 | CPU | CPY | type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1841 | CPU | CPY | type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1842 | CPU | CPY | type_src=f32,type_dst=f32,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1843 | CPU | CPY | type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1844 | CPU | CPY | type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1845 | CPU | CPY | type_src=f32,type_dst=f32,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1846 | CPU | CPY | type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1847 | CPU | CPY | type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1848 | CPU | CPY | type_src=f32,type_dst=f32,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1849 | CPU | CPY | type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1850 | CPU | CPY | type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1851 | CPU | CPY | type_src=f16,type_dst=f16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1852 | CPU | CPY | type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1853 | CPU | CPY | type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1854 | CPU | CPY | type_src=f16,type_dst=f16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1855 | CPU | CPY | type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1856 | CPU | CPY | type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1857 | CPU | CPY | type_src=f16,type_dst=f16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1858 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1859 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1860 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[1,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1861 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1862 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1863 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[2,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1864 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1865 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1866 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[3,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1867 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1868 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1869 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1870 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1871 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1872 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1873 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1874 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1875 | CPU | CPY | type_src=q4_0,type_dst=q4_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1876 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1877 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1878 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1879 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1880 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1881 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1882 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1883 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1884 | CPU | CPY | type_src=q4_1,type_dst=q4_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1885 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1886 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1887 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1888 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1889 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1890 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1891 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1892 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1893 | CPU | CPY | type_src=q5_0,type_dst=q5_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1894 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1895 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1896 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1897 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1898 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1899 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1900 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1901 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1902 | CPU | CPY | type_src=q5_1,type_dst=q5_1,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1903 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1904 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1905 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1906 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1907 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1908 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1909 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1910 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1911 | CPU | CPY | type_src=q8_0,type_dst=q8_0,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1912 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1913 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1914 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1915 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1916 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1917 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1918 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1919 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1920 | CPU | CPY | type_src=q2_K,type_dst=q2_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1921 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1922 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1923 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1924 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1925 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1926 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1927 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1928 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1929 | CPU | CPY | type_src=q3_K,type_dst=q3_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1930 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1931 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1932 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1933 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1934 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1935 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1936 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1937 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1938 | CPU | CPY | type_src=q4_K,type_dst=q4_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1939 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1940 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1941 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1942 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1943 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1944 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1945 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1946 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1947 | CPU | CPY | type_src=q5_K,type_dst=q5_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1948 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1949 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1950 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1951 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1952 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1953 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1954 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1955 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
1956 | CPU | CPY | type_src=q6_K,type_dst=q6_K,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
1957 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1958 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1959 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1960 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1961 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1962 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1963 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1964 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1965 | CPU | CPY | type_src=iq2_xxs,type_dst=iq2_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1966 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1967 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1968 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1969 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1970 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1971 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1972 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1973 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1974 | CPU | CPY | type_src=iq2_xs,type_dst=iq2_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1975 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1976 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1977 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1978 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1979 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1980 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1981 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1982 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1983 | CPU | CPY | type_src=iq2_s,type_dst=iq2_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1984 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1985 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1986 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1987 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1988 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1989 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1990 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1991 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1992 | CPU | CPY | type_src=iq3_xxs,type_dst=iq3_xxs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1993 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1994 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1995 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1996 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1997 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
1998 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
1999 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2000 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2001 | CPU | CPY | type_src=iq1_s,type_dst=iq1_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2002 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2003 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2004 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2005 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2006 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2007 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2008 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2009 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2010 | CPU | CPY | type_src=iq1_m,type_dst=iq1_m,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2011 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2012 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2013 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[32,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2014 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2015 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2016 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[64,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2017 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2018 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2019 | CPU | CPY | type_src=iq4_nl,type_dst=iq4_nl,ne=[96,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2020 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2021 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2022 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2023 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2024 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2025 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2026 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2027 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2028 | CPU | CPY | type_src=iq3_s,type_dst=iq3_s,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 0 | no | CPU |
2029 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2030 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2031 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2032 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2033 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2034 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[512,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2035 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2036 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2037 | CPU | CPY | type_src=iq4_xs,type_dst=iq4_xs,ne=[768,2,3,4],permute_src=[0,3,1,2],permute_dst=[0,2,1,3] | support | 1 | yes | CPU |
2038 | CPU | CPY | type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2039 | CPU | CPY | type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2040 | CPU | CPY | type_src=f16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2041 | CPU | CPY | type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2042 | CPU | CPY | type_src=f16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2043 | CPU | CPY | type_src=f16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2044 | CPU | CPY | type_src=f16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2045 | CPU | CPY | type_src=f16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2046 | CPU | CPY | type_src=f16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2047 | CPU | CPY | type_src=f16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2048 | CPU | CPY | type_src=f16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2049 | CPU | CPY | type_src=f16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2050 | CPU | CPY | type_src=f16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2051 | CPU | CPY | type_src=f16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2052 | CPU | CPY | type_src=f16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2053 | CPU | CPY | type_src=f16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2054 | CPU | CPY | type_src=f16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2055 | CPU | CPY | type_src=f16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2056 | CPU | CPY | type_src=f16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2057 | CPU | CPY | type_src=f16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2058 | CPU | CPY | type_src=f16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2059 | CPU | CPY | type_src=f16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2060 | CPU | CPY | type_src=f16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2061 | CPU | CPY | type_src=f16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2062 | CPU | CPY | type_src=f16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2063 | CPU | CPY | type_src=f16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2064 | CPU | CPY | type_src=f16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2065 | CPU | CPY | type_src=f16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2066 | CPU | CPY | type_src=f16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2067 | CPU | CPY | type_src=f16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2068 | CPU | CPY | type_src=f16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2069 | CPU | CPY | type_src=f16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2070 | CPU | CPY | type_src=f16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2071 | CPU | CPY | type_src=f16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2072 | CPU | CPY | type_src=f16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2073 | CPU | CPY | type_src=f16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2074 | CPU | CPY | type_src=f16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2075 | CPU | CPY | type_src=f16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2076 | CPU | CPY | type_src=f16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2077 | CPU | CPY | type_src=f16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2078 | CPU | CPY | type_src=f16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2079 | CPU | CPY | type_src=f16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2080 | CPU | CPY | type_src=f16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2081 | CPU | CPY | type_src=f16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2082 | CPU | CPY | type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2083 | CPU | CPY | type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2084 | CPU | CPY | type_src=bf16,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2085 | CPU | CPY | type_src=bf16,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2086 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2087 | CPU | CPY | type_src=bf16,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2088 | CPU | CPY | type_src=bf16,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2089 | CPU | CPY | type_src=bf16,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2090 | CPU | CPY | type_src=bf16,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2091 | CPU | CPY | type_src=bf16,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2092 | CPU | CPY | type_src=bf16,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2093 | CPU | CPY | type_src=bf16,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2094 | CPU | CPY | type_src=bf16,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2095 | CPU | CPY | type_src=bf16,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2096 | CPU | CPY | type_src=bf16,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2097 | CPU | CPY | type_src=bf16,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2098 | CPU | CPY | type_src=bf16,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2099 | CPU | CPY | type_src=bf16,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2100 | CPU | CPY | type_src=bf16,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2101 | CPU | CPY | type_src=bf16,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2102 | CPU | CPY | type_src=bf16,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2103 | CPU | CPY | type_src=bf16,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2104 | CPU | CPY | type_src=bf16,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2105 | CPU | CPY | type_src=bf16,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2106 | CPU | CPY | type_src=bf16,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2107 | CPU | CPY | type_src=bf16,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2108 | CPU | CPY | type_src=bf16,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2109 | CPU | CPY | type_src=bf16,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2110 | CPU | CPY | type_src=bf16,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2111 | CPU | CPY | type_src=bf16,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2112 | CPU | CPY | type_src=bf16,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2113 | CPU | CPY | type_src=bf16,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2114 | CPU | CPY | type_src=bf16,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2115 | CPU | CPY | type_src=bf16,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2116 | CPU | CPY | type_src=bf16,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2117 | CPU | CPY | type_src=bf16,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2118 | CPU | CPY | type_src=bf16,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2119 | CPU | CPY | type_src=bf16,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2120 | CPU | CPY | type_src=bf16,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2121 | CPU | CPY | type_src=bf16,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2122 | CPU | CPY | type_src=bf16,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2123 | CPU | CPY | type_src=bf16,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2124 | CPU | CPY | type_src=bf16,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2125 | CPU | CPY | type_src=bf16,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2126 | CPU | CPY | type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2127 | CPU | CPY | type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2128 | CPU | CPY | type_src=f32,type_dst=f16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2129 | CPU | CPY | type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2130 | CPU | CPY | type_src=f32,type_dst=bf16,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2131 | CPU | CPY | type_src=f32,type_dst=bf16,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2132 | CPU | CPY | type_src=f32,type_dst=q4_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2133 | CPU | CPY | type_src=f32,type_dst=q4_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2134 | CPU | CPY | type_src=f32,type_dst=q4_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2135 | CPU | CPY | type_src=f32,type_dst=q4_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2136 | CPU | CPY | type_src=f32,type_dst=q5_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2137 | CPU | CPY | type_src=f32,type_dst=q5_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2138 | CPU | CPY | type_src=f32,type_dst=q5_1,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2139 | CPU | CPY | type_src=f32,type_dst=q5_1,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2140 | CPU | CPY | type_src=f32,type_dst=q8_0,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2141 | CPU | CPY | type_src=f32,type_dst=q8_0,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2142 | CPU | CPY | type_src=f32,type_dst=q2_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2143 | CPU | CPY | type_src=f32,type_dst=q2_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2144 | CPU | CPY | type_src=f32,type_dst=q3_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2145 | CPU | CPY | type_src=f32,type_dst=q3_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2146 | CPU | CPY | type_src=f32,type_dst=q4_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2147 | CPU | CPY | type_src=f32,type_dst=q4_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2148 | CPU | CPY | type_src=f32,type_dst=q5_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2149 | CPU | CPY | type_src=f32,type_dst=q5_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2150 | CPU | CPY | type_src=f32,type_dst=q6_K,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2151 | CPU | CPY | type_src=f32,type_dst=q6_K,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2152 | CPU | CPY | type_src=f32,type_dst=iq2_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2153 | CPU | CPY | type_src=f32,type_dst=iq2_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2154 | CPU | CPY | type_src=f32,type_dst=iq2_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2155 | CPU | CPY | type_src=f32,type_dst=iq2_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2156 | CPU | CPY | type_src=f32,type_dst=iq2_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2157 | CPU | CPY | type_src=f32,type_dst=iq2_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2158 | CPU | CPY | type_src=f32,type_dst=iq3_xxs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2159 | CPU | CPY | type_src=f32,type_dst=iq3_xxs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2160 | CPU | CPY | type_src=f32,type_dst=iq1_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2161 | CPU | CPY | type_src=f32,type_dst=iq1_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2162 | CPU | CPY | type_src=f32,type_dst=iq1_m,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2163 | CPU | CPY | type_src=f32,type_dst=iq1_m,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2164 | CPU | CPY | type_src=f32,type_dst=iq4_nl,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2165 | CPU | CPY | type_src=f32,type_dst=iq4_nl,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2166 | CPU | CPY | type_src=f32,type_dst=iq3_s,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2167 | CPU | CPY | type_src=f32,type_dst=iq3_s,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 0 | no | CPU |
2168 | CPU | CPY | type_src=f32,type_dst=iq4_xs,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2169 | CPU | CPY | type_src=f32,type_dst=iq4_xs,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2170 | CPU | CPY | type_src=f32,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2171 | CPU | CPY | type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2172 | CPU | CPY | type_src=f16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2173 | CPU | CPY | type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2174 | CPU | CPY | type_src=bf16,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2175 | CPU | CPY | type_src=bf16,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2176 | CPU | CPY | type_src=q4_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2177 | CPU | CPY | type_src=q4_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2178 | CPU | CPY | type_src=q4_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2179 | CPU | CPY | type_src=q4_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2180 | CPU | CPY | type_src=q5_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2181 | CPU | CPY | type_src=q5_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2182 | CPU | CPY | type_src=q5_1,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2183 | CPU | CPY | type_src=q5_1,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2184 | CPU | CPY | type_src=q8_0,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2185 | CPU | CPY | type_src=q8_0,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2186 | CPU | CPY | type_src=q2_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2187 | CPU | CPY | type_src=q2_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2188 | CPU | CPY | type_src=q3_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2189 | CPU | CPY | type_src=q3_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2190 | CPU | CPY | type_src=q4_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2191 | CPU | CPY | type_src=q4_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2192 | CPU | CPY | type_src=q5_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2193 | CPU | CPY | type_src=q5_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2194 | CPU | CPY | type_src=q6_K,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2195 | CPU | CPY | type_src=q6_K,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2196 | CPU | CPY | type_src=iq2_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2197 | CPU | CPY | type_src=iq2_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2198 | CPU | CPY | type_src=iq2_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2199 | CPU | CPY | type_src=iq2_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2200 | CPU | CPY | type_src=iq2_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2201 | CPU | CPY | type_src=iq2_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2202 | CPU | CPY | type_src=iq3_xxs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2203 | CPU | CPY | type_src=iq3_xxs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2204 | CPU | CPY | type_src=iq1_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2205 | CPU | CPY | type_src=iq1_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2206 | CPU | CPY | type_src=iq1_m,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2207 | CPU | CPY | type_src=iq1_m,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2208 | CPU | CPY | type_src=iq4_nl,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2209 | CPU | CPY | type_src=iq4_nl,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2210 | CPU | CPY | type_src=iq3_s,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2211 | CPU | CPY | type_src=iq3_s,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2212 | CPU | CPY | type_src=iq4_xs,type_dst=f32,ne=[256,4,4,4],permute_src=[0,0,0,0],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2213 | CPU | CPY | type_src=iq4_xs,type_dst=f32,ne=[256,2,3,4],permute_src=[0,2,1,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2214 | CPU | CPY | type_src=f16,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2215 | CPU | CPY | type_src=f16,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2216 | CPU | CPY | type_src=f32,type_dst=f16,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2217 | CPU | CPY | type_src=f32,type_dst=f32,ne=[256,2,3,4],permute_src=[1,0,2,3],permute_dst=[0,0,0,0] | support | 1 | yes | CPU |
2218 | CPU | CONT | type=f32,ne=[10,10,10,1] | support | 1 | yes | CPU |
2219 | CPU | CONT | type=f32,ne=[2,1,1,1] | support | 1 | yes | CPU |
2220 | CPU | CONT | type=f32,ne=[2,1,3,5] | support | 1 | yes | CPU |
2221 | CPU | CONT | type=f32,ne=[2,3,5,7] | support | 1 | yes | CPU |
2222 | CPU | CONT | type=f16,ne=[2,1,1,1] | support | 1 | yes | CPU |
2223 | CPU | CONT | type=f16,ne=[2,1,3,5] | support | 1 | yes | CPU |
2224 | CPU | CONT | type=f16,ne=[2,3,5,7] | support | 1 | yes | CPU |
2225 | CPU | CONT | type=bf16,ne=[2,1,1,1] | support | 1 | yes | CPU |
2226 | CPU | CONT | type=bf16,ne=[2,1,3,5] | support | 1 | yes | CPU |
2227 | CPU | CONT | type=bf16,ne=[2,3,5,7] | support | 1 | yes | CPU |
2228 | CPU | ADD | type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2229 | CPU | SUB | type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2230 | CPU | MUL | type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2231 | CPU | DIV | type=f16,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2232 | CPU | ADD | type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2233 | CPU | SUB | type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2234 | CPU | MUL | type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2235 | CPU | DIV | type=f16,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2236 | CPU | ADD | type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2237 | CPU | SUB | type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2238 | CPU | MUL | type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2239 | CPU | DIV | type=f16,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2240 | CPU | ADD | type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2241 | CPU | SUB | type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2242 | CPU | MUL | type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2243 | CPU | DIV | type=f16,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2244 | CPU | ADD | type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2245 | CPU | SUB | type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2246 | CPU | MUL | type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2247 | CPU | DIV | type=f16,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2248 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2249 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2250 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2251 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2252 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2253 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2254 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2255 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2256 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2257 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2258 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2259 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2260 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2261 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2262 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2263 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2264 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2265 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2266 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2267 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2268 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2269 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2270 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2271 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2272 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2273 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2274 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2275 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2276 | CPU | ADD | type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2277 | CPU | SUB | type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2278 | CPU | MUL | type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2279 | CPU | DIV | type=f16,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2280 | CPU | ADD | type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2281 | CPU | SUB | type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2282 | CPU | MUL | type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2283 | CPU | DIV | type=f16,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2284 | CPU | ADD | type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2285 | CPU | SUB | type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2286 | CPU | MUL | type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2287 | CPU | DIV | type=f16,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2288 | CPU | ADD | type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2289 | CPU | SUB | type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2290 | CPU | MUL | type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2291 | CPU | DIV | type=f16,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2292 | CPU | ADD | type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2293 | CPU | SUB | type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2294 | CPU | MUL | type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2295 | CPU | DIV | type=f16,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2296 | CPU | ADD | type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2297 | CPU | SUB | type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2298 | CPU | MUL | type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2299 | CPU | DIV | type=f16,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2300 | CPU | ADD | type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2301 | CPU | SUB | type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2302 | CPU | MUL | type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2303 | CPU | DIV | type=f16,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2304 | CPU | ADD | type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2305 | CPU | SUB | type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2306 | CPU | MUL | type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2307 | CPU | DIV | type=f16,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2308 | CPU | ADD | type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2309 | CPU | SUB | type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2310 | CPU | MUL | type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2311 | CPU | DIV | type=f16,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2312 | CPU | ADD | type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2313 | CPU | SUB | type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2314 | CPU | MUL | type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2315 | CPU | DIV | type=f16,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2316 | CPU | ADD | type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2317 | CPU | SUB | type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2318 | CPU | MUL | type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2319 | CPU | DIV | type=f16,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2320 | CPU | ADD | type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2321 | CPU | SUB | type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2322 | CPU | MUL | type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2323 | CPU | DIV | type=f16,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2324 | CPU | ADD | type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2325 | CPU | SUB | type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2326 | CPU | MUL | type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2327 | CPU | DIV | type=f16,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2328 | CPU | ADD | type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2329 | CPU | SUB | type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2330 | CPU | MUL | type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2331 | CPU | DIV | type=f16,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2332 | CPU | ADD | type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2333 | CPU | SUB | type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2334 | CPU | MUL | type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2335 | CPU | DIV | type=f32,ne=[1,1,8,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2336 | CPU | ADD | type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2337 | CPU | SUB | type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2338 | CPU | MUL | type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2339 | CPU | DIV | type=f32,ne=[1,1,1,1],nr=[32,1,1,1],nf=1 | support | 1 | yes | CPU |
2340 | CPU | ADD | type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2341 | CPU | SUB | type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2342 | CPU | MUL | type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2343 | CPU | DIV | type=f32,ne=[1,1,320,320],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2344 | CPU | ADD | type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2345 | CPU | SUB | type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2346 | CPU | MUL | type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2347 | CPU | DIV | type=f32,ne=[10,5,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2348 | CPU | ADD | type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2349 | CPU | SUB | type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2350 | CPU | MUL | type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2351 | CPU | DIV | type=f32,ne=[10,5,4,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2352 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2353 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2354 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2355 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2356 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2357 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2358 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2359 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=1 | support | 1 | yes | CPU |
2360 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2361 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2362 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2363 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,2,1,1],nf=1 | support | 1 | yes | CPU |
2364 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2365 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2366 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2367 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=1 | support | 1 | yes | CPU |
2368 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2369 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2370 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2371 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,1,1,2],nf=1 | support | 1 | yes | CPU |
2372 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2373 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2374 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2375 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=1 | support | 1 | yes | CPU |
2376 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2377 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2378 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2379 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=1 | support | 1 | yes | CPU |
2380 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2381 | CPU | SUB | type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2382 | CPU | MUL | type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2383 | CPU | DIV | type=f32,ne=[10,5,4,3],nr=[2,2,2,2],nf=1 | support | 1 | yes | CPU |
2384 | CPU | ADD | type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2385 | CPU | SUB | type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2386 | CPU | MUL | type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2387 | CPU | DIV | type=f32,ne=[1280,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2388 | CPU | ADD | type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2389 | CPU | SUB | type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2390 | CPU | MUL | type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2391 | CPU | DIV | type=f32,ne=[1280,1,1,1],nr=[1,16,16,1],nf=1 | support | 1 | yes | CPU |
2392 | CPU | ADD | type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2393 | CPU | SUB | type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2394 | CPU | MUL | type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2395 | CPU | DIV | type=f32,ne=[1280,16,16,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2396 | CPU | ADD | type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2397 | CPU | SUB | type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2398 | CPU | MUL | type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2399 | CPU | DIV | type=f32,ne=[1280,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2400 | CPU | ADD | type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2401 | CPU | SUB | type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2402 | CPU | MUL | type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2403 | CPU | DIV | type=f32,ne=[1,1,1280,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2404 | CPU | ADD | type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2405 | CPU | SUB | type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2406 | CPU | MUL | type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2407 | CPU | DIV | type=f32,ne=[16,16,1280,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2408 | CPU | ADD | type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2409 | CPU | SUB | type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2410 | CPU | MUL | type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2411 | CPU | DIV | type=f32,ne=[1,1,1920,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2412 | CPU | ADD | type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2413 | CPU | SUB | type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2414 | CPU | MUL | type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2415 | CPU | DIV | type=f32,ne=[1,1,2560,1],nr=[16,16,1,1],nf=1 | support | 1 | yes | CPU |
2416 | CPU | ADD | type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2417 | CPU | SUB | type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2418 | CPU | MUL | type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2419 | CPU | DIV | type=f32,ne=[1,1,1280,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2420 | CPU | ADD | type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2421 | CPU | SUB | type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2422 | CPU | MUL | type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2423 | CPU | DIV | type=f32,ne=[1,1,1920,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2424 | CPU | ADD | type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2425 | CPU | SUB | type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2426 | CPU | MUL | type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2427 | CPU | DIV | type=f32,ne=[1,1,640,1],nr=[32,32,1,1],nf=1 | support | 1 | yes | CPU |
2428 | CPU | ADD | type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2429 | CPU | SUB | type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2430 | CPU | MUL | type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2431 | CPU | DIV | type=f32,ne=[5120,1,1,1],nr=[1,256,1,1],nf=1 | support | 1 | yes | CPU |
2432 | CPU | ADD | type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2433 | CPU | SUB | type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2434 | CPU | MUL | type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2435 | CPU | DIV | type=f32,ne=[640,1,1,1],nr=[1,1,1,1],nf=1 | support | 1 | yes | CPU |
2436 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[2,1,1,1],nf=2 | support | 1 | yes | CPU |
2437 | CPU | ADD | type=f32,ne=[16,5,4,3],nr=[1,2,1,1],nf=3 | support | 1 | yes | CPU |
2438 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,2,1],nf=4 | support | 1 | yes | CPU |
2439 | CPU | ADD | type=f32,ne=[16,5,4,3],nr=[1,1,1,2],nf=5 | support | 1 | yes | CPU |
2440 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,1,2,2],nf=6 | support | 1 | yes | CPU |
2441 | CPU | ADD | type=f32,ne=[10,5,4,3],nr=[1,2,2,2],nf=7 | support | 1 | yes | CPU |
2442 | CPU | ADD | type=f32,ne=[16,5,4,3],nr=[2,2,2,2],nf=8 | support | 1 | yes | CPU |
2443 | CPU | ADD1 | type=f32,ne=[10,5,4,3] | support | 1 | yes | CPU |
2444 | CPU | SCALE | type=f32,ne=[10,10,10,10],scale=2.000000,bias=0.000000 | support | 1 | yes | CPU |
2445 | CPU | SCALE | type=f32,ne=[10,10,10,10],scale=2.000000,bias=1.000000 | support | 1 | yes | CPU |
2446 | CPU | SILU_BACK | type=f32,ne=[64,5,4,3],eps=0.000001 | support | 1 | yes | CPU |
2447 | CPU | NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000000 | support | 1 | yes | CPU |
2448 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000000 | support | 1 | yes | CPU |
2449 | CPU | NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000000 | support | 1 | yes | CPU |
2450 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000000 | support | 1 | yes | CPU |
2451 | CPU | RMS_NORM_BACK | type=f32,ne=[64,5,4,3],eps=0.000000 | support | 1 | yes | CPU |
2452 | CPU | L2_NORM | type=f32,ne=[64,5,4,3] | support | 1 | yes | CPU |
2453 | CPU | NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000001 | support | 1 | yes | CPU |
2454 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000001 | support | 1 | yes | CPU |
2455 | CPU | NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000001 | support | 1 | yes | CPU |
2456 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000001 | support | 1 | yes | CPU |
2457 | CPU | RMS_NORM_BACK | type=f32,ne=[64,5,4,3],eps=0.000001 | support | 1 | yes | CPU |
2458 | CPU | L2_NORM | type=f32,ne=[64,5,4,3] | support | 1 | yes | CPU |
2459 | CPU | NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000100 | support | 1 | yes | CPU |
2460 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.000100 | support | 1 | yes | CPU |
2461 | CPU | NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000100 | support | 1 | yes | CPU |
2462 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.000100 | support | 1 | yes | CPU |
2463 | CPU | RMS_NORM_BACK | type=f32,ne=[64,5,4,3],eps=0.000100 | support | 1 | yes | CPU |
2464 | CPU | L2_NORM | type=f32,ne=[64,5,4,3] | support | 1 | yes | CPU |
2465 | CPU | NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.100000 | support | 1 | yes | CPU |
2466 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=0,eps=0.100000 | support | 1 | yes | CPU |
2467 | CPU | NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.100000 | support | 1 | yes | CPU |
2468 | CPU | RMS_NORM | type=f32,ne=[64,5,4,3],v=1,eps=0.100000 | support | 1 | yes | CPU |
2469 | CPU | RMS_NORM_BACK | type=f32,ne=[64,5,4,3],eps=0.100000 | support | 1 | yes | CPU |
2470 | CPU | L2_NORM | type=f32,ne=[64,5,4,3] | support | 1 | yes | CPU |
2471 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=0 | support | 1 | yes | CPU |
2472 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000000,broadcast=1 | support | 1 | yes | CPU |
2473 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=0 | support | 1 | yes | CPU |
2474 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000001,broadcast=1 | support | 1 | yes | CPU |
2475 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=0 | support | 1 | yes | CPU |
2476 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.000100,broadcast=1 | support | 1 | yes | CPU |
2477 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=0 | support | 1 | yes | CPU |
2478 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=0.100000,broadcast=1 | support | 1 | yes | CPU |
2479 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=0 | support | 1 | yes | CPU |
2480 | CPU | RMS_NORM_MUL_ADD | type=f32,ne=[64,5,4,3],eps=1.000000,broadcast=1 | support | 1 | yes | CPU |
2481 | CPU | L2_NORM | type=f32,ne=[64,5,4,3] | support | 1 | yes | CPU |
2482 | CPU | SSM_CONV | type=f32,ne_a=[4,1024,1,1],ne_b=[3,1024,1,1] | support | 1 | yes | CPU |
2483 | CPU | SSM_CONV | type=f32,ne_a=[8,1024,1,1],ne_b=[3,1024,1,1] | support | 1 | yes | CPU |
2484 | CPU | SSM_CONV | type=f32,ne_a=[4,1024,4,1],ne_b=[3,1024,1,1] | support | 1 | yes | CPU |
2485 | CPU | SSM_CONV | type=f32,ne_a=[4,1536,1,1],ne_b=[3,1536,1,1] | support | 1 | yes | CPU |
2486 | CPU | SSM_CONV | type=f32,ne_a=[8,1536,1,1],ne_b=[3,1536,1,1] | support | 1 | yes | CPU |
2487 | CPU | SSM_CONV | type=f32,ne_a=[4,1536,4,1],ne_b=[3,1536,1,1] | support | 1 | yes | CPU |
2488 | CPU | SSM_CONV | type=f32,ne_a=[4,2048,1,1],ne_b=[3,2048,1,1] | support | 1 | yes | CPU |
2489 | CPU | SSM_CONV | type=f32,ne_a=[8,2048,1,1],ne_b=[3,2048,1,1] | support | 1 | yes | CPU |
2490 | CPU | SSM_CONV | type=f32,ne_a=[4,2048,4,1],ne_b=[3,2048,1,1] | support | 1 | yes | CPU |
2491 | CPU | SSM_CONV | type=f32,ne_a=[4,1024,1,1],ne_b=[4,1024,1,1] | support | 1 | yes | CPU |
2492 | CPU | SSM_CONV | type=f32,ne_a=[8,1024,1,1],ne_b=[4,1024,1,1] | support | 1 | yes | CPU |
2493 | CPU | SSM_CONV | type=f32,ne_a=[4,1024,4,1],ne_b=[4,1024,1,1] | support | 1 | yes | CPU |
2494 | CPU | SSM_CONV | type=f32,ne_a=[4,1536,1,1],ne_b=[4,1536,1,1] | support | 1 | yes | CPU |
2495 | CPU | SSM_CONV | type=f32,ne_a=[8,1536,1,1],ne_b=[4,1536,1,1] | support | 1 | yes | CPU |
2496 | CPU | SSM_CONV | type=f32,ne_a=[4,1536,4,1],ne_b=[4,1536,1,1] | support | 1 | yes | CPU |
2497 | CPU | SSM_CONV | type=f32,ne_a=[4,2048,1,1],ne_b=[4,2048,1,1] | support | 1 | yes | CPU |
2498 | CPU | SSM_CONV | type=f32,ne_a=[8,2048,1,1],ne_b=[4,2048,1,1] | support | 1 | yes | CPU |
2499 | CPU | SSM_CONV | type=f32,ne_a=[4,2048,4,1],ne_b=[4,2048,1,1] | support | 1 | yes | CPU |
2500 | CPU | SSM_SCAN | type=f32,d_state=16,head_dim=1,n_head=1024,n_group=1,n_seq_tokens=32,n_seqs=4 | support | 1 | yes | CPU |
The file is too large to be shown. View Raw |