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Extend explanation for MDC clock

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This commit is contained in:
Sergio R. Caprile 2022-09-02 15:03:46 -03:00
parent db35e6a427
commit 4a1a26e8b7
2 changed files with 20 additions and 4 deletions
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12
mip/driver_stm32.c
View File

@ -2,10 +2,12 @@
#if MG_ENABLE_MIP && defined(__arm__) #if MG_ENABLE_MIP && defined(__arm__)
// define to your own clock if using external clocking
#if !defined(MG_STM32_CLK_HSE) #if !defined(MG_STM32_CLK_HSE)
#define MG_STM32_CLK_HSE 8000000UL #define MG_STM32_CLK_HSE 8000000UL
#endif #endif
// define to your chip internal clock if different
#if !defined(MG_STM32_CLK_HSI) #if !defined(MG_STM32_CLK_HSI)
#define MG_STM32_CLK_HSI 16000000UL #define MG_STM32_CLK_HSI 16000000UL
#endif #endif
@ -188,8 +190,14 @@ static uint32_t hclk_get(void) {
return ((uint32_t) clk) >> ahbptab[hpre - 8]; return ((uint32_t) clk) >> ahbptab[hpre - 8];
} }
/* Guess CR from HCLK, set to IEEE802.3 max -5% clock drift; /* Guess CR from HCLK:
valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) */ MDC clock is generated from HCLK (AHB); as per 802.3, it must not exceed 2.5MHz
As the AHB clock can be (and usually is) derived from the HSI (internal RC),
and it can go above specs, the datasheets specify a range of frequencies and
activate one of a series of dividers to keep the MDC clock safely below 2.5MHz.
We guess a divider setting based on HCLK with a +5% drift.
If the user uses a different clock from our defaults, needs to set the macros on top
Valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) (both 4.5% worst case drift) */
#define CRDTAB_LEN 6 #define CRDTAB_LEN 6
static const uint8_t crdtab[CRDTAB_LEN][2] = { static const uint8_t crdtab[CRDTAB_LEN][2] = {
// [{setting, div ratio},...] // [{setting, div ratio},...]

12
mongoose.c
View File

@ -5973,10 +5973,12 @@ struct mip_driver mip_driver_enc28j60 = {.init = mip_driver_enc28j60_init,
#if MG_ENABLE_MIP && defined(__arm__) #if MG_ENABLE_MIP && defined(__arm__)
// define to your own clock if using external clocking
#if !defined(MG_STM32_CLK_HSE) #if !defined(MG_STM32_CLK_HSE)
#define MG_STM32_CLK_HSE 8000000UL #define MG_STM32_CLK_HSE 8000000UL
#endif #endif
// define to your chip internal clock if different
#if !defined(MG_STM32_CLK_HSI) #if !defined(MG_STM32_CLK_HSI)
#define MG_STM32_CLK_HSI 16000000UL #define MG_STM32_CLK_HSI 16000000UL
#endif #endif
@ -6159,8 +6161,14 @@ static uint32_t hclk_get(void) {
return ((uint32_t) clk) >> ahbptab[hpre - 8]; return ((uint32_t) clk) >> ahbptab[hpre - 8];
} }
/* Guess CR from HCLK, set to IEEE802.3 max -5% clock drift; /* Guess CR from HCLK:
valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) */ MDC clock is generated from HCLK (AHB); as per 802.3, it must not exceed 2.5MHz
As the AHB clock can be (and usually is) derived from the HSI (internal RC),
and it can go above specs, the datasheets specify a range of frequencies and
activate one of a series of dividers to keep the MDC clock safely below 2.5MHz.
We guess a divider setting based on HCLK with a +5% drift.
If the user uses a different clock from our defaults, needs to set the macros on top
Valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) (both 4.5% worst case drift) */
#define CRDTAB_LEN 6 #define CRDTAB_LEN 6
static const uint8_t crdtab[CRDTAB_LEN][2] = { static const uint8_t crdtab[CRDTAB_LEN][2] = {
// [{setting, div ratio},...] // [{setting, div ratio},...]