mirror of
https://github.com/cesanta/mongoose.git
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220 lines
8.5 KiB
C
220 lines
8.5 KiB
C
#include "mip.h"
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#if MG_ENABLE_MIP && defined(__arm__)
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// define to your own clock if using external clocking
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#if !defined(MG_STM32_CLK_HSE)
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#define MG_STM32_CLK_HSE 8000000UL
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#endif
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// define to your chip internal clock if different
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#if !defined(MG_STM32_CLK_HSI)
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#define MG_STM32_CLK_HSI 16000000UL
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#endif
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struct stm32_eth {
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volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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MACIMR, MACA0HR, MACA0LR, MACA1HR, MACA1LR, MACA2HR, MACA2LR, MACA3HR,
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MACA3LR, RESERVED2[40], MMCCR, MMCRIR, MMCTIR, MMCRIMR, MMCTIMR,
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RESERVED3[14], MMCTGFSCCR, MMCTGFMSCCR, RESERVED4[5], MMCTGFCR,
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RESERVED5[10], MMCRFCECR, MMCRFAECR, RESERVED6[10], MMCRGUFCR,
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RESERVED7[334], PTPTSCR, PTPSSIR, PTPTSHR, PTPTSLR, PTPTSHUR, PTPTSLUR,
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PTPTSAR, PTPTTHR, PTPTTLR, RESERVED8, PTPTSSR, PTPPPSCR, RESERVED9[564],
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DMABMR, DMATPDR, DMARPDR, DMARDLAR, DMATDLAR, DMASR, DMAOMR, DMAIER,
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DMAMFBOCR, DMARSWTR, RESERVED10[8], DMACHTDR, DMACHRDR, DMACHTBAR,
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DMACHRBAR;
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};
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#define ETH ((struct stm32_eth *) (uintptr_t) 0x40028000)
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static void (*s_rx)(void *, size_t, void *); // Recv callback
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static void *s_rxdata; // Recv callback data
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enum { PHY_ADDR = 0, PHY_BCR = 0, PHY_BSR = 1 }; // PHY constants
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static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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static uint32_t hclk_get(void);
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static uint8_t cr_guess(uint32_t hclk);
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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return ETH->MACMIIDR;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ETH->MACMIIDR = val;
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6) | BIT(1);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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}
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static bool mip_driver_stm32_init(uint8_t *mac, void *userdata) {
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = BIT(31); // Own
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s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | BIT(14); // 2nd address chained
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s_rxdesc[i][2] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] =
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(uint32_t) (uintptr_t) s_rxdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][2] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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s_txdesc[i][3] =
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(uint32_t) (uintptr_t) s_txdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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ETH->DMABMR |= BIT(0); // Software reset
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while ((ETH->DMABMR & BIT(0)) != 0) spin(1); // Wait until done
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// NOTE(cpq): we do not use extended descriptor bit 7, and do not use
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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ETH->MACMIIAR = cr_guess(hclk_get()) << 2; // MDC clock
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ETH->MACFCR = BIT(7); // Disable zero quarta pause
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ETH->MACFFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
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ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
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ETH->DMATDLAR = (uint32_t) (uintptr_t) s_txdesc; // RX descriptors
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ETH->DMAIER = BIT(6) | BIT(16); // RIE, NISE
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ETH->MACCR = BIT(2) | BIT(3) | BIT(11) | BIT(14); // RE, TE, Duplex, Fast
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ETH->DMAOMR = BIT(1) | BIT(13) | BIT(21) | BIT(25); // SR, ST, TSF, RSF
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// TODO(cpq): setup MAC filtering
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(void) userdata, (void) mac;
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return true;
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}
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static void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *),
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void *rxdata) {
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s_rx = rx;
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s_rxdata = rxdata;
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}
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static uint32_t s_txno;
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static size_t mip_driver_stm32_tx(const void *buf, size_t len, void *userdata) {
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if (len > sizeof(s_txbuf[s_txno])) {
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printf("%s: frame too big, %ld\n", __func__, (long) len);
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][0] & BIT(31))) {
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printf("%s: no free descr\n", __func__);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] = BIT(20) | BIT(28) | BIT(29) | BIT(30); // Chain,FS,LS
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s_txdesc[s_txno][0] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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uint32_t sr = ETH->DMASR;
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if (sr & BIT(2)) ETH->DMASR = BIT(2), ETH->DMATPDR = 0; // Resume
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if (sr & BIT(5)) ETH->DMASR = BIT(5), ETH->DMATPDR = 0; // if busy
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if (len == 0) printf("E: D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) sr);
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return len;
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(void) userdata;
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}
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static bool mip_driver_stm32_up(void *userdata) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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(void) userdata;
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return bsr & BIT(2) ? 1 : 0;
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}
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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volatile uint32_t sr = ETH->DMASR;
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if (sr & BIT(6)) { // Frame received, loop
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for (uint32_t i = 0; i < ETH_DESC_CNT; i++) {
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if (s_rxdesc[i][0] & BIT(31)) continue;
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uint32_t len = ((s_rxdesc[i][0] >> 16) & (BIT(14) - 1));
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// printf("%lx %lu %lx %lx\n", i, len, s_rxdesc[i][0], sr);
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if (s_rx != NULL) s_rx(s_rxbuf[i], len > 4 ? len - 4 : len, s_rxdata);
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s_rxdesc[i][0] = BIT(31);
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}
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}
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if (sr & BIT(7)) ETH->DMARPDR = 0; // Resume RX
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ETH->DMASR = sr & ~(BIT(2) | BIT(7)); // Clear status
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}
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struct mip_driver mip_driver_stm32 = {.init = mip_driver_stm32_init,
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.tx = mip_driver_stm32_tx,
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.setrx = mip_driver_stm32_setrx,
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.up = mip_driver_stm32_up};
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/* Calculate HCLK from clock settings,
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valid for STM32F74xxx/75xxx (5.3) and STM32F42xxx/43xxx (6.3) */
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static const uint8_t ahbptab[8] = {1, 2, 3, 4, 6, 7, 8, 9}; // log2(div)
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struct rcc {
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volatile uint32_t CR, PLLCFGR, CFGR;
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};
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#define RCC ((struct rcc *) 0x40023800)
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static uint32_t hclk_get(void) {
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uint32_t clk = 0;
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if (RCC->CFGR & (1 << 2)) {
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clk = MG_STM32_CLK_HSE;
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} else if (RCC->CFGR & (1 << 3)) {
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uint32_t vco, m, n, p;
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m = (RCC->PLLCFGR & (0x3FUL << 0)) >> 0;
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n = (RCC->PLLCFGR & (0x1FFUL << 6)) >> 6;
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p = (((RCC->PLLCFGR & (0x03UL << 16)) >> 16) + 1) * 2;
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if (RCC->PLLCFGR & (1UL << 22))
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clk = MG_STM32_CLK_HSE;
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else
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clk = MG_STM32_CLK_HSI;
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vco = (uint32_t)((uint64_t)(((uint32_t) clk * (uint32_t) n)) /
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((uint32_t) m));
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clk = vco / p;
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} else {
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clk = MG_STM32_CLK_HSI;
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}
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int hpre = (RCC->CFGR & (0x0F << 4)) >> 4;
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if (hpre < 8) return clk;
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return ((uint32_t) clk) >> ahbptab[hpre - 8];
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}
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/* Guess CR from HCLK:
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MDC clock is generated from HCLK (AHB); as per 802.3, it must not exceed 2.5MHz
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As the AHB clock can be (and usually is) derived from the HSI (internal RC),
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and it can go above specs, the datasheets specify a range of frequencies and
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activate one of a series of dividers to keep the MDC clock safely below 2.5MHz.
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We guess a divider setting based on HCLK with a +5% drift.
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If the user uses a different clock from our defaults, needs to set the macros on top
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Valid for STM32F74xxx/75xxx (38.8.1) and STM32F42xxx/43xxx (33.8.1) (both 4.5% worst case drift) */
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#define CRDTAB_LEN 6
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static const uint8_t crdtab[CRDTAB_LEN][2] = {
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// [{setting, div ratio},...]
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{2, 16}, {3, 26}, {0, 42}, {1, 62}, {4, 102}, {5, 124},
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};
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static uint8_t cr_guess(uint32_t hclk) {
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MG_DEBUG(("HCLK: %u", hclk));
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if (hclk < 25000000) {
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MG_ERROR(("HCLK too low"));
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return CRDTAB_LEN;
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}
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for (int i = 0; i < CRDTAB_LEN; i++)
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if (hclk / crdtab[i][1] <= 2375000UL) return crdtab[i][0]; // 2.5MHz - 5%
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MG_ERROR(("HCLK too high"));
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return CRDTAB_LEN;
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}
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#endif // MG_ENABLE_MIP
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