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https://github.com/cesanta/mongoose.git
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Remove IMX, imx prefix for NXP
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cpq
parent
2903937cba
commit
2caff93f83
24
mongoose.c
24
mongoose.c
@ -8438,9 +8438,9 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) {
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#endif
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \
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MG_ENABLE_DRIVER_IMXRT1020
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struct imx_rt1020_enet {
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \
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MG_ENABLE_DRIVER_RT1020
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struct rt1020_enet {
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volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3],
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ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR,
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RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2,
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@ -8465,7 +8465,7 @@ struct imx_rt1020_enet {
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};
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#undef ENET
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#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u)
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#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u)
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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@ -8509,9 +8509,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3,
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// it must not exceed 2.5MHz
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// The PHY receives the PLL6-generated 50MHz clock
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static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_imxrt1020_data *d =
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(struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data;
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static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_rt1020_data *d =
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(struct mg_tcpip_driver_rt1020_data *) ifp->driver_data;
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s_ifp = ifp;
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// Init RX descriptors
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@ -8561,7 +8561,7 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
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// Transmit frame
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
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static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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@ -8582,7 +8582,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
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return len;
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}
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static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) {
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static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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bool up = bsr & BIT(2) ? 1 : 0;
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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@ -8620,9 +8620,9 @@ void ENET_IRQHandler(void) {
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// If b24 == 0, descriptors were exhausted and probably frames were dropped
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}
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struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = {
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mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL,
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mg_tcpip_driver_imxrt1020_up};
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struct mg_tcpip_driver mg_tcpip_driver_rt1020 = {
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mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL,
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mg_tcpip_driver_rt1020_up};
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#endif
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@ -1789,7 +1789,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32;
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extern struct mg_tcpip_driver mg_tcpip_driver_w5500;
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extern struct mg_tcpip_driver mg_tcpip_driver_tm4c;
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extern struct mg_tcpip_driver mg_tcpip_driver_stm32h;
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extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020;
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extern struct mg_tcpip_driver mg_tcpip_driver_rt1020;
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extern struct mg_tcpip_driver mg_tcpip_driver_same54;
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// Drivers that require SPI, can use this SPI abstraction
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@ -1802,7 +1802,7 @@ struct mg_tcpip_spi {
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#endif
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struct mg_tcpip_driver_imxrt1020_data {
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struct mg_tcpip_driver_rt1020_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
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@ -1,8 +1,8 @@
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#include "tcpip.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \
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MG_ENABLE_DRIVER_IMXRT1020
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struct imx_rt1020_enet {
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \
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MG_ENABLE_DRIVER_RT1020
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struct rt1020_enet {
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volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3],
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ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR,
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RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2,
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@ -27,7 +27,7 @@ struct imx_rt1020_enet {
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};
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#undef ENET
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#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u)
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#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u)
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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@ -71,9 +71,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3,
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// it must not exceed 2.5MHz
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// The PHY receives the PLL6-generated 50MHz clock
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static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_imxrt1020_data *d =
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(struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data;
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static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_rt1020_data *d =
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(struct mg_tcpip_driver_rt1020_data *) ifp->driver_data;
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s_ifp = ifp;
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// Init RX descriptors
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@ -123,7 +123,7 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
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// Transmit frame
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
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static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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@ -144,7 +144,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
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return len;
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}
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static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) {
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static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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bool up = bsr & BIT(2) ? 1 : 0;
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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@ -182,8 +182,8 @@ void ENET_IRQHandler(void) {
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// If b24 == 0, descriptors were exhausted and probably frames were dropped
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}
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struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = {
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mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL,
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mg_tcpip_driver_imxrt1020_up};
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struct mg_tcpip_driver mg_tcpip_driver_rt1020 = {
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mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL,
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mg_tcpip_driver_rt1020_up};
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#endif
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@ -1,6 +1,6 @@
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#pragma once
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struct mg_tcpip_driver_imxrt1020_data {
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struct mg_tcpip_driver_rt1020_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
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@ -55,7 +55,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32;
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extern struct mg_tcpip_driver mg_tcpip_driver_w5500;
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extern struct mg_tcpip_driver mg_tcpip_driver_tm4c;
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extern struct mg_tcpip_driver mg_tcpip_driver_stm32h;
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extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020;
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extern struct mg_tcpip_driver mg_tcpip_driver_rt1020;
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extern struct mg_tcpip_driver mg_tcpip_driver_same54;
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// Drivers that require SPI, can use this SPI abstraction
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