From 2caff93f837b236cca314291fa76ee2b9bdcc60a Mon Sep 17 00:00:00 2001 From: cpq Date: Tue, 24 Oct 2023 17:30:22 +0100 Subject: [PATCH] Remove IMX, imx prefix for NXP --- mongoose.c | 26 +++++++++++++------------- mongoose.h | 4 ++-- src/drivers/rt1020.c | 26 +++++++++++++------------- src/drivers/rt1020.h | 2 +- src/net_builtin.h | 2 +- 5 files changed, 30 insertions(+), 30 deletions(-) diff --git a/mongoose.c b/mongoose.c index 29d29484..b768dbad 100644 --- a/mongoose.c +++ b/mongoose.c @@ -8438,9 +8438,9 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) { #endif -#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ - MG_ENABLE_DRIVER_IMXRT1020 -struct imx_rt1020_enet { +#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \ + MG_ENABLE_DRIVER_RT1020 +struct rt1020_enet { volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, @@ -8465,7 +8465,7 @@ struct imx_rt1020_enet { }; #undef ENET -#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u) +#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u) #undef BIT #define BIT(x) ((uint32_t) 1 << (x)) @@ -8509,9 +8509,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { // MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, // it must not exceed 2.5MHz // The PHY receives the PLL6-generated 50MHz clock -static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { - struct mg_tcpip_driver_imxrt1020_data *d = - (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; +static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) { + struct mg_tcpip_driver_rt1020_data *d = + (struct mg_tcpip_driver_rt1020_data *) ifp->driver_data; s_ifp = ifp; // Init RX descriptors @@ -8561,8 +8561,8 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { // Transmit frame static uint32_t s_txno; -static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, - struct mg_tcpip_if *ifp) { +static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len, + struct mg_tcpip_if *ifp) { if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { MG_ERROR(("Frame too big, %ld", (long) len)); len = 0; // fail @@ -8582,7 +8582,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, return len; } -static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { +static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) { uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); bool up = bsr & BIT(2) ? 1 : 0; if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up @@ -8620,9 +8620,9 @@ void ENET_IRQHandler(void) { // If b24 == 0, descriptors were exhausted and probably frames were dropped } -struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { - mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, - mg_tcpip_driver_imxrt1020_up}; +struct mg_tcpip_driver mg_tcpip_driver_rt1020 = { + mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL, + mg_tcpip_driver_rt1020_up}; #endif diff --git a/mongoose.h b/mongoose.h index fc9eb7ac..f03f5174 100644 --- a/mongoose.h +++ b/mongoose.h @@ -1789,7 +1789,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32; extern struct mg_tcpip_driver mg_tcpip_driver_w5500; extern struct mg_tcpip_driver mg_tcpip_driver_tm4c; extern struct mg_tcpip_driver mg_tcpip_driver_stm32h; -extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020; +extern struct mg_tcpip_driver mg_tcpip_driver_rt1020; extern struct mg_tcpip_driver mg_tcpip_driver_same54; // Drivers that require SPI, can use this SPI abstraction @@ -1802,7 +1802,7 @@ struct mg_tcpip_spi { #endif -struct mg_tcpip_driver_imxrt1020_data { +struct mg_tcpip_driver_rt1020_data { // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) diff --git a/src/drivers/rt1020.c b/src/drivers/rt1020.c index c96fb98b..6a8ed78b 100644 --- a/src/drivers/rt1020.c +++ b/src/drivers/rt1020.c @@ -1,8 +1,8 @@ #include "tcpip.h" -#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ - MG_ENABLE_DRIVER_IMXRT1020 -struct imx_rt1020_enet { +#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \ + MG_ENABLE_DRIVER_RT1020 +struct rt1020_enet { volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, @@ -27,7 +27,7 @@ struct imx_rt1020_enet { }; #undef ENET -#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u) +#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u) #undef BIT #define BIT(x) ((uint32_t) 1 << (x)) @@ -71,9 +71,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) { // MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, // it must not exceed 2.5MHz // The PHY receives the PLL6-generated 50MHz clock -static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { - struct mg_tcpip_driver_imxrt1020_data *d = - (struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; +static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) { + struct mg_tcpip_driver_rt1020_data *d = + (struct mg_tcpip_driver_rt1020_data *) ifp->driver_data; s_ifp = ifp; // Init RX descriptors @@ -123,8 +123,8 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { // Transmit frame static uint32_t s_txno; -static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, - struct mg_tcpip_if *ifp) { +static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len, + struct mg_tcpip_if *ifp) { if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { MG_ERROR(("Frame too big, %ld", (long) len)); len = 0; // fail @@ -144,7 +144,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, return len; } -static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { +static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) { uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); bool up = bsr & BIT(2) ? 1 : 0; if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up @@ -182,8 +182,8 @@ void ENET_IRQHandler(void) { // If b24 == 0, descriptors were exhausted and probably frames were dropped } -struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { - mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, - mg_tcpip_driver_imxrt1020_up}; +struct mg_tcpip_driver mg_tcpip_driver_rt1020 = { + mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL, + mg_tcpip_driver_rt1020_up}; #endif diff --git a/src/drivers/rt1020.h b/src/drivers/rt1020.h index f1a725ea..a355cec1 100644 --- a/src/drivers/rt1020.h +++ b/src/drivers/rt1020.h @@ -1,6 +1,6 @@ #pragma once -struct mg_tcpip_driver_imxrt1020_data { +struct mg_tcpip_driver_rt1020_data { // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) diff --git a/src/net_builtin.h b/src/net_builtin.h index 4ea2346d..4bd43207 100644 --- a/src/net_builtin.h +++ b/src/net_builtin.h @@ -55,7 +55,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32; extern struct mg_tcpip_driver mg_tcpip_driver_w5500; extern struct mg_tcpip_driver mg_tcpip_driver_tm4c; extern struct mg_tcpip_driver mg_tcpip_driver_stm32h; -extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020; +extern struct mg_tcpip_driver mg_tcpip_driver_rt1020; extern struct mg_tcpip_driver mg_tcpip_driver_same54; // Drivers that require SPI, can use this SPI abstraction