feat add memory_barrier
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parent
52a4e711b5
commit
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@ -185,6 +185,7 @@ set(TILE_SRCS
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"tile/base/thread/rw_mutex.cc"
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"tile/base/thread/scoped_lock.cc"
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"tile/base/thread/spinlock.cc"
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"tile/base/memory_barrier.cc"
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"tile/fiber/detail/fiber.cc"
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"tile/io/detail/eintr_safe.cc"
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"tile/io/native/acceptor.cc"
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45
tile/base/memory_barrier.cc
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45
tile/base/memory_barrier.cc
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@ -0,0 +1,45 @@
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#include "tile/base/memory_barrier.h"
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#include <mutex>
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#include <sys/mman.h>
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#include "tile/base/logging.h"
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#include "tile/base/never_destroyed.h"
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namespace tile {
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namespace internal {
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namespace {
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void *
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CreateOneByteDummyPage()
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{
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auto ptr = mmap(nullptr, 1, PROT_READ, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
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TILE_PCHECK(ptr, "Cannot create dummy page for asymmetric memory barrier.");
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(void) mlock(ptr, 1);
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return ptr;
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}
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void
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HomemadeMembarrier()
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{
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static void *dummy_page = CreateOneByteDummyPage();
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MemoryBarrier();
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static NeverDestroyed<std::mutex> lock;
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std::lock_guard<std::mutex> _(*lock);
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TILE_PCHECK(mprotect(dummy_page, 1, PROT_READ | PROT_WRITE) == 0, "Cannot protect dummy page.");
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*static_cast<char volatile *>(dummy_page) = 0;
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TILE_PCHECK(mprotect(dummy_page, 1, PROT_READ) == 0);
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MemoryBarrier();
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}
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}// namespace
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void
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AsymmetricBarrierHeavy()
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{
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HomemadeMembarrier();
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}
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}// namespace internal
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}// namespace tile
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45
tile/base/memory_barrier.h
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45
tile/base/memory_barrier.h
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@ -0,0 +1,45 @@
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#ifndef DOWNLINK__3PARTY_TILE_TILE_BASE_MEMORY_BARRIER_H
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#define DOWNLINK__3PARTY_TILE_TILE_BASE_MEMORY_BARRIER_H
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#pragma once
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#include <atomic>
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namespace tile {
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namespace internal {
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inline void
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CompilerBarrier()
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{
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std::atomic_signal_fence(std::memory_order_seq_cst);
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}
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inline void
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ReadBarrier()
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{
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std::atomic_thread_fence(std::memory_order_seq_cst);
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}
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inline void
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WriteBarrier()
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{
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std::atomic_thread_fence(std::memory_order_seq_cst);
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}
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inline void
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MemoryBarrier()
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{
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std::atomic_thread_fence(std::memory_order_seq_cst);
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}
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inline void
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AsymmetricBarrierLight()
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{
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CompilerBarrier();
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}
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void AsymmetricBarrierHeavy();
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}// namespace internal
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}// namespace tile
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#endif// DOWNLINK__3PARTY_TILE_TILE_BASE_MEMORY_BARRIER_H
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