luoyu-intel d08c20edde [SYCL] Fix the sub group size of Intel (#8106) ...

* use warp_size macro for all sycl kernels

* fix mask of permute_sub_group_by_xor

* fix rms_norm with correct warp number

* fix rms_norm_f32/group_norm_f32

* move norm to norm.cpp file

* fix quantize bug

* fix mmvq's batch size

2024-07-02 10:16:00 +08:00

..

dpct

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backend.hpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

common.cpp

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common.hpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

convert.cpp

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convert.hpp

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dequantize.hpp

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dmmv.cpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

dmmv.hpp

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mmq.cpp

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mmq.hpp

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mmvq.cpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

mmvq.hpp

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norm.cpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

norm.hpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

presets.hpp

[SYCL] Fix the sub group size of Intel (#8106)

2024-07-02 10:16:00 +08:00

rope.cpp

[SYCL] Update SYCL-Rope op and Refactor (#8157)

2024-07-01 19:39:06 +08:00

rope.hpp

[SYCL] Update SYCL-Rope op and Refactor (#8157)

2024-07-01 19:39:06 +08:00

vecdotq.hpp

CUDA: refactor and optimize IQ MMVQ (#8215)

2024-07-01 20:39:06 +02:00