ea175e28f8
This change authored by vadimskipin and submitted via:
https://github.com/google/leveldb/pull/309
Changes made to support iOS builds and other architectures
without support for SSE 4.2.
db_bench reports original crc32 speed at:
crc32c : 3.610 micros/op; 1082.0 MB/s (4K per op)
with this change performance has increased to:
crc32c : 0.843 micros/op; 4633.6 MB/s (4K per op)
-------------
Created by MOE: https://github.com/google/moe
MOE_MIGRATED_REVID=148694935
126 lines
3.3 KiB
C++
126 lines
3.3 KiB
C++
// Copyright 2016 The LevelDB Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file. See the AUTHORS file for names of contributors.
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//
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// A portable implementation of crc32c, optimized to handle
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// four bytes at a time.
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//
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// In a separate source file to allow this accelerated CRC32C function to be
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// compiled with the appropriate compiler flags to enable x86 SSE 4.2
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// instructions.
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#include <stdint.h>
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#include <string.h>
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#include "port/port.h"
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#if defined(LEVELDB_PLATFORM_POSIX_SSE)
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#if defined(_MSC_VER)
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#include <intrin.h>
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#elif defined(__GNUC__) && defined(__SSE4_2__)
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#include <nmmintrin.h>
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#include <cpuid.h>
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#endif
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#endif // defined(LEVELDB_PLATFORM_POSIX_SSE)
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namespace leveldb {
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namespace port {
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#if defined(LEVELDB_PLATFORM_POSIX_SSE)
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// Used to fetch a naturally-aligned 32-bit word in little endian byte-order
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static inline uint32_t LE_LOAD32(const uint8_t *p) {
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// SSE is x86 only, so ensured that |p| is always little-endian.
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uint32_t word;
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memcpy(&word, p, sizeof(word));
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return word;
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}
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// Used to fetch a naturally-aligned 64-bit word in little endian byte-order
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static inline uint64_t LE_LOAD64(const uint8_t *p) {
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uint64_t dword;
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memcpy(&dword, p, sizeof(dword));
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return dword;
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}
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static inline bool HaveSSE42() {
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#if defined(_MSC_VER)
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int cpu_info[4];
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__cpuid(cpu_info, 1);
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return (cpu_info[2] & (1 << 20)) != 0;
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#elif defined(__GNUC__)
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unsigned int eax, ebx, ecx, edx;
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__get_cpuid(1, &eax, &ebx, &ecx, &edx);
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return (ecx & (1 << 20)) != 0;
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#else
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return false;
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#endif
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}
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#endif // defined(LEVELDB_PLATFORM_POSIX_SSE)
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// For further improvements see Intel publication at:
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// http://download.intel.com/design/intarch/papers/323405.pdf
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uint32_t AcceleratedCRC32C(uint32_t crc, const char* buf, size_t size) {
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#if !defined(LEVELDB_PLATFORM_POSIX_SSE)
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return 0;
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#else
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static bool have = HaveSSE42();
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if (!have) {
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return 0;
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}
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const uint8_t *p = reinterpret_cast<const uint8_t *>(buf);
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const uint8_t *e = p + size;
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uint32_t l = crc ^ 0xffffffffu;
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#define STEP1 do { \
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l = _mm_crc32_u8(l, *p++); \
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} while (0)
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#define STEP4 do { \
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l = _mm_crc32_u32(l, LE_LOAD32(p)); \
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p += 4; \
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} while (0)
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#define STEP8 do { \
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l = _mm_crc32_u64(l, LE_LOAD64(p)); \
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p += 8; \
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} while (0)
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if (size > 16) {
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// Process unaligned bytes
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for (unsigned int i = reinterpret_cast<uintptr_t>(p) % 8; i; --i) {
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STEP1;
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}
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// _mm_crc32_u64 is only available on x64.
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#if defined(_M_X64) || defined(__x86_64__)
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// Process 8 bytes at a time
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while ((e-p) >= 8) {
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STEP8;
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}
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// Process 4 bytes at a time
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if ((e-p) >= 4) {
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STEP4;
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}
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#else // !(defined(_M_X64) || defined(__x86_64__))
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// Process 4 bytes at a time
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while ((e-p) >= 4) {
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STEP4;
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}
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#endif // defined(_M_X64) || defined(__x86_64__)
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}
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// Process the last few bytes
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while (p != e) {
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STEP1;
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}
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#undef STEP8
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#undef STEP4
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#undef STEP1
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return l ^ 0xffffffffu;
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#endif // defined(LEVELDB_PLATFORM_POSIX_SSE)
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}
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} // namespace port
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} // namespace leveldb
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