86 lines
4.7 KiB
JSON
86 lines
4.7 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xc3",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
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"PDIR_COUNTER": "na",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.",
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"SampleAfterValue": "20003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000001",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000001",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000001",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000001",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000002",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0XB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x2104000002",
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"Offcore": "1",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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}
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] |