118 lines
4.9 KiB
JSON
118 lines
4.9 KiB
JSON
[
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{
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"EventCode": "0x20036",
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"EventName": "PM_BR_2PATH",
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"BriefDescription": "Branches that are not strongly biased"
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},
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{
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"EventCode": "0x40056",
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"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
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"BriefDescription": "Local memory above threshold for LSU medium"
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},
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{
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"EventCode": "0x40118",
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"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
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"BriefDescription": "Combined Intervention event"
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},
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{
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"EventCode": "0x4F148",
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"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
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"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x301E8",
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"EventName": "PM_THRESH_EXC_64",
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"BriefDescription": "Threshold counter exceeded a value of 64"
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},
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{
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"EventCode": "0x4E04E",
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"EventName": "PM_DPTEG_FROM_L3MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x40050",
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"EventName": "PM_SYS_PUMP_MPRED_RTY",
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"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
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},
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{
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"EventCode": "0x1F14E",
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"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x4D018",
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"EventName": "PM_CMPLU_STALL_BRU",
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"BriefDescription": "Completion stall due to a Branch Unit"
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},
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{
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"EventCode": "0x45052",
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"EventName": "PM_4FLOP_CMPL",
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"BriefDescription": "4 FLOP instruction completed"
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},
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{
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"EventCode": "0x3D142",
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"EventName": "PM_MRK_DATA_FROM_LMEM",
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"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
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},
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{
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"EventCode": "0x4C01E",
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"EventName": "PM_CMPLU_STALL_CRYPTO",
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"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
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},
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{
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"EventCode": "0x3000C",
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"EventName": "PM_FREQ_DOWN",
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"BriefDescription": "Power Management: Below Threshold B"
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},
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{
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"EventCode": "0x4D128",
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"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
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"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
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},
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{
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"EventCode": "0x4D054",
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"EventName": "PM_8FLOP_CMPL",
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"BriefDescription": "8 FLOP instruction completed"
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},
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{
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"EventCode": "0x10026",
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"EventName": "PM_TABLEWALK_CYC",
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"BriefDescription": "Cycles when an instruction tablewalk is active"
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},
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{
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"EventCode": "0x2C012",
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"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
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"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
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},
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{
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"EventCode": "0x2E04C",
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"EventName": "PM_DPTEG_FROM_MEMORY",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x3F142",
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"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x4F142",
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"EventName": "PM_MRK_DPTEG_FROM_L3",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x10060",
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"EventName": "PM_TM_TRANS_RUN_CYC",
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"BriefDescription": "run cycles in transactional state"
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},
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{
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"EventCode": "0x1E04C",
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"EventName": "PM_DPTEG_FROM_LL4",
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"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
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},
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{
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"EventCode": "0x45050",
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"EventName": "PM_1FLOP_CMPL",
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"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
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}
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]
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