251 lines
8.0 KiB
C
251 lines
8.0 KiB
C
#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
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/* special clients */
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#define TEGRA186_SID_INVALID 0x00
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#define TEGRA186_SID_PASSTHROUGH 0x7f
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/* host1x clients */
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#define TEGRA186_SID_HOST1X 0x01
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#define TEGRA186_SID_CSI 0x02
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#define TEGRA186_SID_VIC 0x03
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#define TEGRA186_SID_VI 0x04
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#define TEGRA186_SID_ISP 0x05
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#define TEGRA186_SID_NVDEC 0x06
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#define TEGRA186_SID_NVENC 0x07
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#define TEGRA186_SID_NVJPG 0x08
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#define TEGRA186_SID_NVDISPLAY 0x09
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#define TEGRA186_SID_TSEC 0x0a
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#define TEGRA186_SID_TSECB 0x0b
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#define TEGRA186_SID_SE 0x0c
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#define TEGRA186_SID_SE1 0x0d
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#define TEGRA186_SID_SE2 0x0e
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#define TEGRA186_SID_SE3 0x0f
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/* GPU clients */
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#define TEGRA186_SID_GPU 0x10
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/* other SoC clients */
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#define TEGRA186_SID_AFI 0x11
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#define TEGRA186_SID_HDA 0x12
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#define TEGRA186_SID_ETR 0x13
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#define TEGRA186_SID_EQOS 0x14
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#define TEGRA186_SID_UFSHC 0x15
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#define TEGRA186_SID_AON 0x16
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#define TEGRA186_SID_SDMMC4 0x17
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#define TEGRA186_SID_SDMMC3 0x18
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#define TEGRA186_SID_SDMMC2 0x19
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#define TEGRA186_SID_SDMMC1 0x1a
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#define TEGRA186_SID_XUSB_HOST 0x1b
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#define TEGRA186_SID_XUSB_DEV 0x1c
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#define TEGRA186_SID_SATA 0x1d
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#define TEGRA186_SID_APE 0x1e
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#define TEGRA186_SID_SCE 0x1f
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/* GPC DMA clients */
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#define TEGRA186_SID_GPCDMA_0 0x20
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#define TEGRA186_SID_GPCDMA_1 0x21
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#define TEGRA186_SID_GPCDMA_2 0x22
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#define TEGRA186_SID_GPCDMA_3 0x23
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#define TEGRA186_SID_GPCDMA_4 0x24
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#define TEGRA186_SID_GPCDMA_5 0x25
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#define TEGRA186_SID_GPCDMA_6 0x26
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#define TEGRA186_SID_GPCDMA_7 0x27
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/* APE DMA clients */
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#define TEGRA186_SID_APE_1 0x28
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#define TEGRA186_SID_APE_2 0x29
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/* camera RTCPU */
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#define TEGRA186_SID_RCE 0x2a
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/* camera RTCPU on host1x address space */
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#define TEGRA186_SID_RCE_1X 0x2b
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/* APE DMA clients */
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#define TEGRA186_SID_APE_3 0x2c
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/* camera RTCPU running on APE */
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#define TEGRA186_SID_APE_CAM 0x2d
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#define TEGRA186_SID_APE_CAM_1X 0x2e
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/*
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* The BPMP has its SID value hardcoded in the firmware. Changing it requires
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* considerable effort.
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*/
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#define TEGRA186_SID_BPMP 0x32
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/* for SMMU tests */
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#define TEGRA186_SID_SMMU_TEST 0x33
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/* host1x virtualization channels */
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#define TEGRA186_SID_HOST1X_CTX0 0x38
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#define TEGRA186_SID_HOST1X_CTX1 0x39
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#define TEGRA186_SID_HOST1X_CTX2 0x3a
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#define TEGRA186_SID_HOST1X_CTX3 0x3b
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#define TEGRA186_SID_HOST1X_CTX4 0x3c
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#define TEGRA186_SID_HOST1X_CTX5 0x3d
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#define TEGRA186_SID_HOST1X_CTX6 0x3e
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#define TEGRA186_SID_HOST1X_CTX7 0x3f
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/* host1x command buffers */
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#define TEGRA186_SID_HOST1X_VM0 0x40
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#define TEGRA186_SID_HOST1X_VM1 0x41
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#define TEGRA186_SID_HOST1X_VM2 0x42
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#define TEGRA186_SID_HOST1X_VM3 0x43
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#define TEGRA186_SID_HOST1X_VM4 0x44
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#define TEGRA186_SID_HOST1X_VM5 0x45
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#define TEGRA186_SID_HOST1X_VM6 0x46
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#define TEGRA186_SID_HOST1X_VM7 0x47
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/* SE data buffers */
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#define TEGRA186_SID_SE_VM0 0x48
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#define TEGRA186_SID_SE_VM1 0x49
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#define TEGRA186_SID_SE_VM2 0x4a
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#define TEGRA186_SID_SE_VM3 0x4b
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#define TEGRA186_SID_SE_VM4 0x4c
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#define TEGRA186_SID_SE_VM5 0x4d
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#define TEGRA186_SID_SE_VM6 0x4e
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#define TEGRA186_SID_SE_VM7 0x4f
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/*
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* memory client IDs
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*/
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/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
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#define TEGRA186_MEMORY_CLIENT_PTCR 0x00
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/* PCIE reads */
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#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e
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/* High-definition audio (HDA) reads */
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#define TEGRA186_MEMORY_CLIENT_HDAR 0x15
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/* Host channel data reads */
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#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16
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#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c
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/* SATA reads */
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#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f
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/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27
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#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b
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/* PCIE writes */
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#define TEGRA186_MEMORY_CLIENT_AFIW 0x31
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/* High-definition audio (HDA) writes */
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#define TEGRA186_MEMORY_CLIENT_HDAW 0x35
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/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
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#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39
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/* SATA writes */
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#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d
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/* ISP Read client for Crossbar A */
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#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44
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/* ISP Write client for Crossbar A */
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#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46
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/* ISP Write client Crossbar B */
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#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47
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/* XUSB reads */
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#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a
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/* XUSB_HOST writes */
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#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b
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/* XUSB reads */
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#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c
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/* XUSB_DEV writes */
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#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d
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/* TSEC Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54
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/* TSEC Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55
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/* 3D, ltcx reads instance 0 */
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#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58
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/* 3D, ltcx writes instance 0 */
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#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59
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/* sdmmca memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60
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/* sdmmcbmemory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61
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/* sdmmc memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62
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/* sdmmcd memory read client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63
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/* sdmmca memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64
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/* sdmmcb memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65
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/* sdmmc memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66
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/* sdmmcd memory write client */
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#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67
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#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c
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#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d
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/* VI Write client */
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#define TEGRA186_MEMORY_CLIENT_VIW 0x72
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#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78
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#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79
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/* Audio Processing (APE) engine reads */
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#define TEGRA186_MEMORY_CLIENT_APER 0x7a
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/* Audio Processing (APE) engine writes */
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#define TEGRA186_MEMORY_CLIENT_APEW 0x7b
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#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e
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#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f
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/* SE Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_SESRD 0x80
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/* SE Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_SESWR 0x81
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/* ETR reads */
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#define TEGRA186_MEMORY_CLIENT_ETRR 0x84
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/* ETR writes */
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#define TEGRA186_MEMORY_CLIENT_ETRW 0x85
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/* TSECB Memory Return Data Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86
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/* TSECB Memory Write Client Description */
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#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87
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/* 3D, ltcx reads instance 1 */
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#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88
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/* 3D, ltcx writes instance 1 */
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#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89
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/* AXI Switch read client */
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#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c
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/* AXI Switch write client */
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#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d
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/* EQOS read client */
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#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e
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/* EQOS write client */
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#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f
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/* UFSHC read client */
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#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90
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/* UFSHC write client */
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#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91
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/* NVDISPLAY read client */
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#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92
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/* BPMP read client */
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#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93
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/* BPMP write client */
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#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94
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/* BPMPDMA read client */
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#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95
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/* BPMPDMA write client */
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#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96
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/* AON read client */
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#define TEGRA186_MEMORY_CLIENT_AONR 0x97
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/* AON write client */
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#define TEGRA186_MEMORY_CLIENT_AONW 0x98
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/* AONDMA read client */
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#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99
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/* AONDMA write client */
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#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a
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/* SCE read client */
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#define TEGRA186_MEMORY_CLIENT_SCER 0x9b
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/* SCE write client */
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#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c
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/* SCEDMA read client */
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#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d
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/* SCEDMA write client */
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#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e
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/* APEDMA read client */
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#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f
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/* APEDMA write client */
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#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0
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/* NVDISPLAY read client instance 2 */
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#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1
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#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2
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#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3
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#endif
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