229 lines
6.5 KiB
C
229 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT8516_H
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#define _DT_BINDINGS_CLK_MT8516_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_APLL1 4
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#define CLK_APMIXED_APLL2 5
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#define CLK_APMIXED_NR_CLK 6
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/* INFRACFG */
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#define CLK_IFR_MUX1_SEL 0
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#define CLK_IFR_ETH_25M_SEL 1
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#define CLK_IFR_I2C0_SEL 2
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#define CLK_IFR_I2C1_SEL 3
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#define CLK_IFR_I2C2_SEL 4
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#define CLK_IFR_NR_CLK 5
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/* TOPCKGEN */
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#define CLK_TOP_CLK_NULL 0
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#define CLK_TOP_I2S_INFRA_BCK 1
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#define CLK_TOP_MEMPLL 2
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#define CLK_TOP_DMPLL 3
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#define CLK_TOP_MAINPLL_D2 4
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#define CLK_TOP_MAINPLL_D4 5
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#define CLK_TOP_MAINPLL_D8 6
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#define CLK_TOP_MAINPLL_D16 7
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#define CLK_TOP_MAINPLL_D11 8
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#define CLK_TOP_MAINPLL_D22 9
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#define CLK_TOP_MAINPLL_D3 10
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#define CLK_TOP_MAINPLL_D6 11
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#define CLK_TOP_MAINPLL_D12 12
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#define CLK_TOP_MAINPLL_D5 13
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#define CLK_TOP_MAINPLL_D10 14
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#define CLK_TOP_MAINPLL_D20 15
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#define CLK_TOP_MAINPLL_D40 16
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#define CLK_TOP_MAINPLL_D7 17
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#define CLK_TOP_MAINPLL_D14 18
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#define CLK_TOP_UNIVPLL_D2 19
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#define CLK_TOP_UNIVPLL_D4 20
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#define CLK_TOP_UNIVPLL_D8 21
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#define CLK_TOP_UNIVPLL_D16 22
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#define CLK_TOP_UNIVPLL_D3 23
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#define CLK_TOP_UNIVPLL_D6 24
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#define CLK_TOP_UNIVPLL_D12 25
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#define CLK_TOP_UNIVPLL_D24 26
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#define CLK_TOP_UNIVPLL_D5 27
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#define CLK_TOP_UNIVPLL_D20 28
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#define CLK_TOP_MMPLL380M 29
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#define CLK_TOP_MMPLL_D2 30
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#define CLK_TOP_MMPLL_200M 31
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#define CLK_TOP_USB_PHY48M 32
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#define CLK_TOP_APLL1 33
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#define CLK_TOP_APLL1_D2 34
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#define CLK_TOP_APLL1_D4 35
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#define CLK_TOP_APLL1_D8 36
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#define CLK_TOP_APLL2 37
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#define CLK_TOP_APLL2_D2 38
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#define CLK_TOP_APLL2_D4 39
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#define CLK_TOP_APLL2_D8 40
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#define CLK_TOP_CLK26M 41
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#define CLK_TOP_CLK26M_D2 42
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#define CLK_TOP_AHB_INFRA_D2 43
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#define CLK_TOP_NFI1X 44
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#define CLK_TOP_ETH_D2 45
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#define CLK_TOP_THEM 46
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#define CLK_TOP_APDMA 47
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#define CLK_TOP_I2C0 48
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#define CLK_TOP_I2C1 49
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#define CLK_TOP_AUXADC1 50
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#define CLK_TOP_NFI 51
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#define CLK_TOP_NFIECC 52
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#define CLK_TOP_DEBUGSYS 53
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#define CLK_TOP_PWM 54
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#define CLK_TOP_UART0 55
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#define CLK_TOP_UART1 56
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#define CLK_TOP_BTIF 57
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#define CLK_TOP_USB 58
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#define CLK_TOP_FLASHIF_26M 59
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#define CLK_TOP_AUXADC2 60
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#define CLK_TOP_I2C2 61
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#define CLK_TOP_MSDC0 62
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#define CLK_TOP_MSDC1 63
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#define CLK_TOP_NFI2X 64
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#define CLK_TOP_PMICWRAP_AP 65
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#define CLK_TOP_SEJ 66
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#define CLK_TOP_MEMSLP_DLYER 67
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#define CLK_TOP_SPI 68
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#define CLK_TOP_APXGPT 69
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#define CLK_TOP_AUDIO 70
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#define CLK_TOP_PMICWRAP_MD 71
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#define CLK_TOP_PMICWRAP_CONN 72
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#define CLK_TOP_PMICWRAP_26M 73
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#define CLK_TOP_AUX_ADC 74
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#define CLK_TOP_AUX_TP 75
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#define CLK_TOP_MSDC2 76
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#define CLK_TOP_RBIST 77
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#define CLK_TOP_NFI_BUS 78
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#define CLK_TOP_GCE 79
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#define CLK_TOP_TRNG 80
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#define CLK_TOP_SEJ_13M 81
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#define CLK_TOP_AES 82
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#define CLK_TOP_PWM_B 83
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#define CLK_TOP_PWM1_FB 84
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#define CLK_TOP_PWM2_FB 85
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#define CLK_TOP_PWM3_FB 86
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#define CLK_TOP_PWM4_FB 87
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#define CLK_TOP_PWM5_FB 88
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#define CLK_TOP_USB_1P 89
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#define CLK_TOP_FLASHIF_FREERUN 90
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#define CLK_TOP_66M_ETH 91
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#define CLK_TOP_133M_ETH 92
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#define CLK_TOP_FETH_25M 93
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#define CLK_TOP_FETH_50M 94
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#define CLK_TOP_FLASHIF_AXI 95
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#define CLK_TOP_USBIF 96
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#define CLK_TOP_UART2 97
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#define CLK_TOP_BSI 98
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#define CLK_TOP_RG_SPINOR 99
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#define CLK_TOP_RG_MSDC2 100
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#define CLK_TOP_RG_ETH 101
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#define CLK_TOP_RG_AUD1 102
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#define CLK_TOP_RG_AUD2 103
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#define CLK_TOP_RG_AUD_ENGEN1 104
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#define CLK_TOP_RG_AUD_ENGEN2 105
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#define CLK_TOP_RG_I2C 106
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#define CLK_TOP_RG_PWM_INFRA 107
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#define CLK_TOP_RG_AUD_SPDIF_IN 108
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#define CLK_TOP_RG_UART2 109
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#define CLK_TOP_RG_BSI 110
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#define CLK_TOP_RG_DBG_ATCLK 111
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#define CLK_TOP_RG_NFIECC 112
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#define CLK_TOP_RG_APLL1_D2_EN 113
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#define CLK_TOP_RG_APLL1_D4_EN 114
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#define CLK_TOP_RG_APLL1_D8_EN 115
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#define CLK_TOP_RG_APLL2_D2_EN 116
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#define CLK_TOP_RG_APLL2_D4_EN 117
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#define CLK_TOP_RG_APLL2_D8_EN 118
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#define CLK_TOP_APLL12_DIV0 119
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#define CLK_TOP_APLL12_DIV1 120
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#define CLK_TOP_APLL12_DIV2 121
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#define CLK_TOP_APLL12_DIV3 122
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#define CLK_TOP_APLL12_DIV4 123
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#define CLK_TOP_APLL12_DIV4B 124
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#define CLK_TOP_APLL12_DIV5 125
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#define CLK_TOP_APLL12_DIV5B 126
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#define CLK_TOP_APLL12_DIV6 127
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#define CLK_TOP_UART0_SEL 128
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#define CLK_TOP_EMI_DDRPHY_SEL 129
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#define CLK_TOP_AHB_INFRA_SEL 130
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#define CLK_TOP_MSDC0_SEL 131
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#define CLK_TOP_UART1_SEL 132
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#define CLK_TOP_MSDC1_SEL 133
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#define CLK_TOP_PMICSPI_SEL 134
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#define CLK_TOP_QAXI_AUD26M_SEL 135
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#define CLK_TOP_AUD_INTBUS_SEL 136
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#define CLK_TOP_NFI2X_PAD_SEL 137
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#define CLK_TOP_NFI1X_PAD_SEL 138
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#define CLK_TOP_DDRPHYCFG_SEL 139
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#define CLK_TOP_USB_78M_SEL 140
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#define CLK_TOP_SPINOR_SEL 141
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#define CLK_TOP_MSDC2_SEL 142
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#define CLK_TOP_ETH_SEL 143
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#define CLK_TOP_AUD1_SEL 144
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#define CLK_TOP_AUD2_SEL 145
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#define CLK_TOP_AUD_ENGEN1_SEL 146
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#define CLK_TOP_AUD_ENGEN2_SEL 147
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#define CLK_TOP_I2C_SEL 148
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#define CLK_TOP_AUD_I2S0_M_SEL 149
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#define CLK_TOP_AUD_I2S1_M_SEL 150
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#define CLK_TOP_AUD_I2S2_M_SEL 151
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#define CLK_TOP_AUD_I2S3_M_SEL 152
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#define CLK_TOP_AUD_I2S4_M_SEL 153
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#define CLK_TOP_AUD_I2S5_M_SEL 154
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#define CLK_TOP_AUD_SPDIF_B_SEL 155
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#define CLK_TOP_PWM_SEL 156
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#define CLK_TOP_SPI_SEL 157
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#define CLK_TOP_AUD_SPDIFIN_SEL 158
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#define CLK_TOP_UART2_SEL 159
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#define CLK_TOP_BSI_SEL 160
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#define CLK_TOP_DBG_ATCLK_SEL 161
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#define CLK_TOP_CSW_NFIECC_SEL 162
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#define CLK_TOP_NFIECC_SEL 163
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#define CLK_TOP_APLL12_CK_DIV0 164
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#define CLK_TOP_APLL12_CK_DIV1 165
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#define CLK_TOP_APLL12_CK_DIV2 166
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#define CLK_TOP_APLL12_CK_DIV3 167
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#define CLK_TOP_APLL12_CK_DIV4 168
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#define CLK_TOP_APLL12_CK_DIV4B 169
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#define CLK_TOP_APLL12_CK_DIV5 170
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#define CLK_TOP_APLL12_CK_DIV5B 171
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#define CLK_TOP_APLL12_CK_DIV6 172
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#define CLK_TOP_USB_78M 173
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#define CLK_TOP_MSDC0_INFRA 174
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#define CLK_TOP_MSDC1_INFRA 175
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#define CLK_TOP_MSDC2_INFRA 176
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#define CLK_TOP_NR_CLK 177
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/* AUDSYS */
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#define CLK_AUD_AFE 0
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#define CLK_AUD_I2S 1
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#define CLK_AUD_22M 2
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#define CLK_AUD_24M 3
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#define CLK_AUD_INTDIR 4
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#define CLK_AUD_APLL2_TUNER 5
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#define CLK_AUD_APLL_TUNER 6
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#define CLK_AUD_HDMI 7
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#define CLK_AUD_SPDF 8
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#define CLK_AUD_ADC 9
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#define CLK_AUD_DAC 10
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#define CLK_AUD_DAC_PREDIS 11
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#define CLK_AUD_TML 12
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#define CLK_AUD_NR_CLK 13
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#endif /* _DT_BINDINGS_CLK_MT8516_H */
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