122 lines
3.0 KiB
C
122 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* camss.h
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*
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* Qualcomm MSM Camera Subsystem - Core
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*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2015-2018 Linaro Ltd.
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*/
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#ifndef QC_MSM_CAMSS_H
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#define QC_MSM_CAMSS_H
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#include <linux/device.h>
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#include <linux/types.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#include <media/media-device.h>
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#include <media/media-entity.h>
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#include "camss-csid.h"
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#include "camss-csiphy.h"
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#include "camss-ispif.h"
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#include "camss-vfe.h"
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#define to_camss(ptr_module) \
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container_of(ptr_module, struct camss, ptr_module)
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#define to_device(ptr_module) \
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(to_camss(ptr_module)->dev)
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#define module_pointer(ptr_module, index) \
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((const struct ptr_module##_device (*)[]) &(ptr_module[-(index)]))
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#define to_camss_index(ptr_module, index) \
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container_of(module_pointer(ptr_module, index), \
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struct camss, ptr_module)
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#define to_device_index(ptr_module, index) \
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(to_camss_index(ptr_module, index)->dev)
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#define CAMSS_RES_MAX 17
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struct resources {
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char *regulator[CAMSS_RES_MAX];
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char *clock[CAMSS_RES_MAX];
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u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX];
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char *reg[CAMSS_RES_MAX];
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char *interrupt[CAMSS_RES_MAX];
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};
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struct resources_ispif {
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char *clock[CAMSS_RES_MAX];
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char *clock_for_reset[CAMSS_RES_MAX];
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char *reg[CAMSS_RES_MAX];
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char *interrupt;
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};
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enum pm_domain {
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PM_DOMAIN_VFE0 = 0,
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PM_DOMAIN_VFE1 = 1,
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PM_DOMAIN_GEN1_COUNT = 2, /* CAMSS series of ISPs */
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PM_DOMAIN_VFELITE = 2, /* VFELITE / TOP GDSC */
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PM_DOMAIN_GEN2_COUNT = 3, /* Titan series of ISPs */
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};
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enum camss_version {
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CAMSS_8x16,
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CAMSS_8x96,
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CAMSS_660,
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CAMSS_845,
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};
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struct camss {
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enum camss_version version;
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struct v4l2_device v4l2_dev;
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struct v4l2_async_notifier notifier;
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struct media_device media_dev;
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struct device *dev;
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int csiphy_num;
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struct csiphy_device *csiphy;
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int csid_num;
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struct csid_device *csid;
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struct ispif_device *ispif;
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int vfe_num;
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struct vfe_device *vfe;
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atomic_t ref_count;
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struct device *genpd[PM_DOMAIN_GEN2_COUNT];
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struct device_link *genpd_link[PM_DOMAIN_GEN2_COUNT];
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};
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struct camss_camera_interface {
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u8 csiphy_id;
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struct csiphy_csi2_cfg csi2;
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};
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struct camss_async_subdev {
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struct v4l2_async_subdev asd; /* must be first */
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struct camss_camera_interface interface;
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};
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struct camss_clock {
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struct clk *clk;
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const char *name;
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u32 *freq;
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u32 nfreqs;
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};
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void camss_add_clock_margin(u64 *rate);
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int camss_enable_clocks(int nclocks, struct camss_clock *clock,
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struct device *dev);
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void camss_disable_clocks(int nclocks, struct camss_clock *clock);
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struct media_entity *camss_find_sensor(struct media_entity *entity);
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s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
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unsigned int lanes);
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int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock);
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int camss_pm_domain_on(struct camss *camss, int id);
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void camss_pm_domain_off(struct camss *camss, int id);
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void camss_delete(struct camss *camss);
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#endif /* QC_MSM_CAMSS_H */
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