477 lines
14 KiB
C
477 lines
14 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv40.h"
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#include "regs.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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#include <engine/fifo.h>
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u64
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nv40_gr_units(struct nvkm_gr *gr)
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{
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return nvkm_rd32(gr->engine.subdev.device, 0x1540);
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}
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/*******************************************************************************
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* Graphics object classes
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******************************************************************************/
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static int
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nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
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int align, struct nvkm_gpuobj **pgpuobj)
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{
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int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align,
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false, parent, pgpuobj);
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if (ret == 0) {
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nvkm_kmap(*pgpuobj);
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nvkm_wo32(*pgpuobj, 0x00, object->oclass);
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nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
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nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
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#ifdef __BIG_ENDIAN
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nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000);
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#endif
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nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
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nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
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nvkm_done(*pgpuobj);
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}
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return ret;
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}
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const struct nvkm_object_func
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nv40_gr_object = {
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.bind = nv40_gr_object_bind,
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};
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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static int
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nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
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int align, struct nvkm_gpuobj **pgpuobj)
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{
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struct nv40_gr_chan *chan = nv40_gr_chan(object);
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struct nv40_gr *gr = chan->gr;
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int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
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align, true, parent, pgpuobj);
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if (ret == 0) {
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chan->inst = (*pgpuobj)->addr;
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nvkm_kmap(*pgpuobj);
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nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
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nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4);
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nvkm_done(*pgpuobj);
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}
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return ret;
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}
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static int
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nv40_gr_chan_fini(struct nvkm_object *object, bool suspend)
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{
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struct nv40_gr_chan *chan = nv40_gr_chan(object);
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struct nv40_gr *gr = chan->gr;
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 inst = 0x01000000 | chan->inst >> 4;
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int ret = 0;
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nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
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if (nvkm_rd32(device, 0x40032c) == inst) {
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if (suspend) {
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nvkm_wr32(device, 0x400720, 0x00000000);
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nvkm_wr32(device, 0x400784, inst);
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nvkm_mask(device, 0x400310, 0x00000020, 0x00000020);
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nvkm_mask(device, 0x400304, 0x00000001, 0x00000001);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x400300) & 0x00000001))
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break;
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) < 0) {
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u32 insn = nvkm_rd32(device, 0x400308);
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nvkm_warn(subdev, "ctxprog timeout %08x\n", insn);
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ret = -EBUSY;
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}
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}
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nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000);
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}
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if (nvkm_rd32(device, 0x400330) == inst)
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nvkm_mask(device, 0x400330, 0x01000000, 0x00000000);
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nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
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return ret;
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}
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static void *
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nv40_gr_chan_dtor(struct nvkm_object *object)
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{
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struct nv40_gr_chan *chan = nv40_gr_chan(object);
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unsigned long flags;
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spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
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list_del(&chan->head);
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spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
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return chan;
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}
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static const struct nvkm_object_func
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nv40_gr_chan = {
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.dtor = nv40_gr_chan_dtor,
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.fini = nv40_gr_chan_fini,
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.bind = nv40_gr_chan_bind,
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};
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int
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nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
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const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
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{
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struct nv40_gr *gr = nv40_gr(base);
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struct nv40_gr_chan *chan;
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unsigned long flags;
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object);
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chan->gr = gr;
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chan->fifo = fifoch;
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*pobject = &chan->object;
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spin_lock_irqsave(&chan->gr->base.engine.lock, flags);
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list_add(&chan->head, &gr->chan);
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spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags);
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return 0;
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}
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static void
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nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
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{
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struct nv40_gr *gr = nv40_gr(base);
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struct nvkm_device *device = gr->base.engine.subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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unsigned long flags;
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nvkm_fifo_pause(fifo, &flags);
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nv04_gr_idle(&gr->base);
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switch (device->chipset) {
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case 0x40:
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
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nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
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switch (device->chipset) {
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case 0x40:
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case 0x45:
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nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
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nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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case 0x41:
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case 0x42:
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case 0x43:
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nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
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nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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default:
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break;
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}
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break;
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case 0x47:
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case 0x49:
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case 0x4b:
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nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
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nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
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nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
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nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
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break;
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default:
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WARN_ON(1);
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break;
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}
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nvkm_fifo_start(fifo, &flags);
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}
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void
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nv40_gr_intr(struct nvkm_gr *base)
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{
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struct nv40_gr *gr = nv40_gr(base);
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struct nv40_gr_chan *temp, *chan = NULL;
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
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u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
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u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
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u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff;
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u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
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u32 subc = (addr & 0x00070000) >> 16;
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
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u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;
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u32 show = stat;
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char msg[128], src[128], sta[128];
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unsigned long flags;
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spin_lock_irqsave(&gr->base.engine.lock, flags);
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list_for_each_entry(temp, &gr->chan, head) {
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if (temp->inst >> 4 == inst) {
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chan = temp;
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list_del(&chan->head);
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list_add(&chan->head, &gr->chan);
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break;
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}
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}
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if (stat & NV_PGRAPH_INTR_ERROR) {
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if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
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nvkm_mask(device, 0x402000, 0, 0);
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}
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}
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nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
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nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
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if (show) {
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nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
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nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
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nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
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nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
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"nstatus %08x [%s] ch %d [%08x %s] subc %d "
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"class %04x mthd %04x data %08x\n",
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show, msg, nsource, src, nstatus, sta,
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chan ? chan->fifo->chid : -1, inst << 4,
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chan ? chan->fifo->object.client->name : "unknown",
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subc, class, mthd, data);
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}
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spin_unlock_irqrestore(&gr->base.engine.lock, flags);
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}
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int
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nv40_gr_init(struct nvkm_gr *base)
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{
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struct nv40_gr *gr = nv40_gr(base);
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struct nvkm_device *device = gr->base.engine.subdev.device;
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int ret, i, j;
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u32 vramsz;
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/* generate and upload context program */
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ret = nv40_grctx_init(device, &gr->size);
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if (ret)
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return ret;
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/* No context present currently */
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nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
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nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
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nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
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nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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j = nvkm_rd32(device, 0x1540) & 0xff;
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if (j) {
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for (i = 0; !(j & 1); j >>= 1, i++)
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;
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nvkm_wr32(device, 0x405000, i);
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}
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if (device->chipset == 0x40) {
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nvkm_wr32(device, 0x4009b0, 0x83280fff);
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nvkm_wr32(device, 0x4009b4, 0x000000a0);
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} else {
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nvkm_wr32(device, 0x400820, 0x83280eff);
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nvkm_wr32(device, 0x400824, 0x000000a0);
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}
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switch (device->chipset) {
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case 0x40:
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case 0x45:
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nvkm_wr32(device, 0x4009b8, 0x0078e366);
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nvkm_wr32(device, 0x4009bc, 0x0000014c);
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break;
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case 0x41:
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case 0x42: /* pciid also 0x00Cx */
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/* case 0x0120: XXX (pciid) */
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nvkm_wr32(device, 0x400828, 0x007596ff);
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nvkm_wr32(device, 0x40082c, 0x00000108);
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break;
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case 0x43:
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nvkm_wr32(device, 0x400828, 0x0072cb77);
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nvkm_wr32(device, 0x40082c, 0x00000108);
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break;
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case 0x44:
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case 0x46: /* G72 */
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case 0x4a:
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case 0x4c: /* G7x-based C51 */
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case 0x4e:
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nvkm_wr32(device, 0x400860, 0);
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nvkm_wr32(device, 0x400864, 0);
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break;
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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nvkm_wr32(device, 0x400828, 0x07830610);
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nvkm_wr32(device, 0x40082c, 0x0000016A);
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break;
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default:
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break;
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}
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nvkm_wr32(device, 0x400b38, 0x2ffff800);
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nvkm_wr32(device, 0x400b3c, 0x00006000);
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/* Tiling related stuff. */
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switch (device->chipset) {
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case 0x44:
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case 0x4a:
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nvkm_wr32(device, 0x400bc4, 0x1003d888);
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nvkm_wr32(device, 0x400bbc, 0xb7a7b500);
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break;
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case 0x46:
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nvkm_wr32(device, 0x400bc4, 0x0000e024);
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nvkm_wr32(device, 0x400bbc, 0xb7a7b520);
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break;
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case 0x4c:
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case 0x4e:
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case 0x67:
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nvkm_wr32(device, 0x400bc4, 0x1003d888);
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nvkm_wr32(device, 0x400bbc, 0xb7a7b540);
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break;
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default:
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break;
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}
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/* begin RAM config */
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vramsz = device->func->resource_size(device, 1) - 1;
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switch (device->chipset) {
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case 0x40:
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nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
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nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204));
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nvkm_wr32(device, 0x400820, 0);
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nvkm_wr32(device, 0x400824, 0);
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nvkm_wr32(device, 0x400864, vramsz);
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nvkm_wr32(device, 0x400868, vramsz);
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break;
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default:
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switch (device->chipset) {
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case 0x41:
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case 0x42:
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case 0x43:
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case 0x45:
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case 0x4e:
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case 0x44:
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case 0x4a:
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nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204));
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break;
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default:
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nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204));
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break;
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}
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nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204));
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nvkm_wr32(device, 0x400840, 0);
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nvkm_wr32(device, 0x400844, 0);
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nvkm_wr32(device, 0x4008A0, vramsz);
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nvkm_wr32(device, 0x4008A4, vramsz);
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break;
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}
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return 0;
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}
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int
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nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
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enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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struct nv40_gr *gr;
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if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
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return -ENOMEM;
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*pgr = &gr->base;
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INIT_LIST_HEAD(&gr->chan);
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return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
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}
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static const struct nvkm_gr_func
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nv40_gr = {
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.init = nv40_gr_init,
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.intr = nv40_gr_intr,
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.tile = nv40_gr_tile,
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.units = nv40_gr_units,
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.chan_new = nv40_gr_chan_new,
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.sclass = {
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{ -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
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{ -1, -1, 0x0019, &nv40_gr_object }, /* clip */
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{ -1, -1, 0x0030, &nv40_gr_object }, /* null */
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{ -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
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{ -1, -1, 0x0043, &nv40_gr_object }, /* rop */
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{ -1, -1, 0x0044, &nv40_gr_object }, /* patt */
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{ -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
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{ -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
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{ -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
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{ -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
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{ -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
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{ -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
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{ -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
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{ -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
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{ -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
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{ -1, -1, 0x4097, &nv40_gr_object }, /* curie */
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{}
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}
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};
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int
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nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return nv40_gr_new_(&nv40_gr, device, type, inst, pgr);
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}
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