377 lines
12 KiB
C
377 lines
12 KiB
C
// SPDX-License-Identifier: MIT
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#include "nv20.h"
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#include "regs.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <engine/fifo.h>
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#include <engine/fifo/chan.h>
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#include <subdev/fb.h>
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#include <subdev/timer.h>
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/*******************************************************************************
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* PGRAPH context
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******************************************************************************/
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int
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nv20_gr_chan_init(struct nvkm_object *object)
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{
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struct nv20_gr_chan *chan = nv20_gr_chan(object);
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struct nv20_gr *gr = chan->gr;
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u32 inst = nvkm_memory_addr(chan->inst);
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nvkm_kmap(gr->ctxtab);
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nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
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nvkm_done(gr->ctxtab);
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return 0;
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}
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int
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nv20_gr_chan_fini(struct nvkm_object *object, bool suspend)
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{
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struct nv20_gr_chan *chan = nv20_gr_chan(object);
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struct nv20_gr *gr = chan->gr;
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 inst = nvkm_memory_addr(chan->inst);
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int chid = -1;
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nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
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if (nvkm_rd32(device, 0x400144) & 0x00010000)
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chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
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if (chan->chid == chid) {
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nvkm_wr32(device, 0x400784, inst >> 4);
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nvkm_wr32(device, 0x400788, 0x00000002);
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nvkm_msec(device, 2000,
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if (!nvkm_rd32(device, 0x400700))
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break;
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);
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nvkm_wr32(device, 0x400144, 0x10000000);
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nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
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}
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nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
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nvkm_kmap(gr->ctxtab);
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nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
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nvkm_done(gr->ctxtab);
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return 0;
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}
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void *
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nv20_gr_chan_dtor(struct nvkm_object *object)
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{
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struct nv20_gr_chan *chan = nv20_gr_chan(object);
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nvkm_memory_unref(&chan->inst);
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return chan;
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}
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static const struct nvkm_object_func
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nv20_gr_chan = {
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.dtor = nv20_gr_chan_dtor,
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.init = nv20_gr_chan_init,
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.fini = nv20_gr_chan_fini,
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};
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static int
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nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
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const struct nvkm_oclass *oclass, struct nvkm_object **pobject)
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{
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struct nv20_gr *gr = nv20_gr(base);
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struct nv20_gr_chan *chan;
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int ret, i;
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object);
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chan->gr = gr;
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chan->chid = fifoch->chid;
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*pobject = &chan->object;
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ret = nvkm_memory_new(gr->base.engine.subdev.device,
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NVKM_MEM_TARGET_INST, 0x37f0, 16, true,
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&chan->inst);
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if (ret)
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return ret;
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nvkm_kmap(chan->inst);
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nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
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nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
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nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
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nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
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nvkm_wo32(chan->inst, 0x047c, 0x00000101);
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nvkm_wo32(chan->inst, 0x0490, 0x00000111);
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nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
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for (i = 0x04d4; i <= 0x04e0; i += 4)
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nvkm_wo32(chan->inst, i, 0x00030303);
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for (i = 0x04f4; i <= 0x0500; i += 4)
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nvkm_wo32(chan->inst, i, 0x00080000);
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for (i = 0x050c; i <= 0x0518; i += 4)
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nvkm_wo32(chan->inst, i, 0x01012000);
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for (i = 0x051c; i <= 0x0528; i += 4)
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nvkm_wo32(chan->inst, i, 0x000105b8);
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for (i = 0x052c; i <= 0x0538; i += 4)
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nvkm_wo32(chan->inst, i, 0x00080008);
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for (i = 0x055c; i <= 0x0598; i += 4)
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nvkm_wo32(chan->inst, i, 0x07ff0000);
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nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff);
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nvkm_wo32(chan->inst, 0x05fc, 0x00000001);
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nvkm_wo32(chan->inst, 0x0604, 0x00004000);
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nvkm_wo32(chan->inst, 0x0610, 0x00000001);
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nvkm_wo32(chan->inst, 0x0618, 0x00040000);
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nvkm_wo32(chan->inst, 0x061c, 0x00010000);
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for (i = 0x1c1c; i <= 0x248c; i += 16) {
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nvkm_wo32(chan->inst, (i + 0), 0x10700ff9);
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nvkm_wo32(chan->inst, (i + 4), 0x0436086c);
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nvkm_wo32(chan->inst, (i + 8), 0x000c001b);
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}
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nvkm_wo32(chan->inst, 0x281c, 0x3f800000);
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nvkm_wo32(chan->inst, 0x2830, 0x3f800000);
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nvkm_wo32(chan->inst, 0x285c, 0x40000000);
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nvkm_wo32(chan->inst, 0x2860, 0x3f800000);
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nvkm_wo32(chan->inst, 0x2864, 0x3f000000);
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nvkm_wo32(chan->inst, 0x286c, 0x40000000);
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nvkm_wo32(chan->inst, 0x2870, 0x3f800000);
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nvkm_wo32(chan->inst, 0x2878, 0xbf800000);
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nvkm_wo32(chan->inst, 0x2880, 0xbf800000);
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nvkm_wo32(chan->inst, 0x34a4, 0x000fe000);
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nvkm_wo32(chan->inst, 0x3530, 0x000003f8);
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nvkm_wo32(chan->inst, 0x3540, 0x002fe000);
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for (i = 0x355c; i <= 0x3578; i += 4)
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nvkm_wo32(chan->inst, i, 0x001c527c);
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nvkm_done(chan->inst);
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return 0;
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}
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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void
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nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
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{
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struct nv20_gr *gr = nv20_gr(base);
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struct nvkm_device *device = gr->base.engine.subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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unsigned long flags;
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nvkm_fifo_pause(fifo, &flags);
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nv04_gr_idle(&gr->base);
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nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
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if (device->chipset != 0x34) {
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nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
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}
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nvkm_fifo_start(fifo, &flags);
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}
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void
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nv20_gr_intr(struct nvkm_gr *base)
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{
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struct nv20_gr *gr = nv20_gr(base);
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_fifo_chan *chan;
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u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
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u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
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u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
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u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
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u32 chid = (addr & 0x01f00000) >> 20;
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u32 subc = (addr & 0x00070000) >> 16;
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u32 mthd = (addr & 0x00001ffc);
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u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
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u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
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u32 show = stat;
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char msg[128], src[128], sta[128];
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unsigned long flags;
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chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags);
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nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
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nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
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if (show) {
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nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show);
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nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource);
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nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus);
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nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] "
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"nstatus %08x [%s] ch %d [%s] subc %d "
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"class %04x mthd %04x data %08x\n",
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show, msg, nsource, src, nstatus, sta, chid,
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chan ? chan->object.client->name : "unknown",
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subc, class, mthd, data);
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}
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nvkm_fifo_chan_put(device->fifo, flags, &chan);
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}
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int
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nv20_gr_oneinit(struct nvkm_gr *base)
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{
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struct nv20_gr *gr = nv20_gr(base);
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return nvkm_memory_new(gr->base.engine.subdev.device,
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NVKM_MEM_TARGET_INST, 32 * 4, 16,
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true, &gr->ctxtab);
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}
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int
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nv20_gr_init(struct nvkm_gr *base)
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{
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struct nv20_gr *gr = nv20_gr(base);
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 tmp, vramsz;
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int i;
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nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
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nvkm_memory_addr(gr->ctxtab) >> 4);
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if (device->chipset == 0x20) {
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
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for (i = 0; i < 15; i++)
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
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nvkm_msec(device, 2000,
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if (!nvkm_rd32(device, 0x400700))
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break;
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);
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} else {
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
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for (i = 0; i < 32; i++)
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
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nvkm_msec(device, 2000,
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if (!nvkm_rd32(device, 0x400700))
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break;
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);
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}
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nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
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nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
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nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
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nvkm_wr32(device, 0x40009C , 0x00000040);
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if (device->chipset >= 0x25) {
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nvkm_wr32(device, 0x400890, 0x00a8cfff);
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nvkm_wr32(device, 0x400610, 0x304B1FB6);
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nvkm_wr32(device, 0x400B80, 0x1cbd3883);
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nvkm_wr32(device, 0x400B84, 0x44000000);
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nvkm_wr32(device, 0x400098, 0x40000080);
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nvkm_wr32(device, 0x400B88, 0x000000ff);
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} else {
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nvkm_wr32(device, 0x400880, 0x0008c7df);
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nvkm_wr32(device, 0x400094, 0x00000005);
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nvkm_wr32(device, 0x400B80, 0x45eae20e);
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nvkm_wr32(device, 0x400B84, 0x24000000);
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nvkm_wr32(device, 0x400098, 0x00000040);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
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}
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nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
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nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
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nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
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tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
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nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
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tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
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nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
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/* begin RAM config */
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vramsz = device->func->resource_size(device, 1) - 1;
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nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
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nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
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nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
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nvkm_wr32(device, 0x400820, 0);
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nvkm_wr32(device, 0x400824, 0);
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nvkm_wr32(device, 0x400864, vramsz - 1);
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nvkm_wr32(device, 0x400868, vramsz - 1);
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/* interesting.. the below overwrites some of the tile setup above.. */
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nvkm_wr32(device, 0x400B20, 0x00000000);
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nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
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nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
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nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
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nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
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nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
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return 0;
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}
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void *
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nv20_gr_dtor(struct nvkm_gr *base)
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{
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struct nv20_gr *gr = nv20_gr(base);
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nvkm_memory_unref(&gr->ctxtab);
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return gr;
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}
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int
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nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
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enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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struct nv20_gr *gr;
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if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
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return -ENOMEM;
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*pgr = &gr->base;
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return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
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}
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static const struct nvkm_gr_func
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nv20_gr = {
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.dtor = nv20_gr_dtor,
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.oneinit = nv20_gr_oneinit,
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.init = nv20_gr_init,
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.intr = nv20_gr_intr,
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.tile = nv20_gr_tile,
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.chan_new = nv20_gr_chan_new,
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.sclass = {
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{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
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{ -1, -1, 0x0019, &nv04_gr_object }, /* clip */
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{ -1, -1, 0x0030, &nv04_gr_object }, /* null */
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{ -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */
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{ -1, -1, 0x0043, &nv04_gr_object }, /* rop */
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{ -1, -1, 0x0044, &nv04_gr_object }, /* patt */
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{ -1, -1, 0x004a, &nv04_gr_object }, /* gdi */
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{ -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */
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{ -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */
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{ -1, -1, 0x0089, &nv04_gr_object }, /* sifm */
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{ -1, -1, 0x008a, &nv04_gr_object }, /* ifc */
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{ -1, -1, 0x0096, &nv04_gr_object }, /* celcius */
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{ -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */
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{ -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */
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{ -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */
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{}
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}
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};
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int
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nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return nv20_gr_new_(&nv20_gr, device, type, inst, pgr);
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}
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