99 lines
2.1 KiB
C
99 lines
2.1 KiB
C
#ifndef __NVFW_PMU_H__
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#define __NVFW_PMU_H__
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struct nv_pmu_args {
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u32 reserved;
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u32 freq_hz;
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u32 trace_size;
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u32 trace_dma_base;
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u16 trace_dma_base1;
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u8 trace_dma_offset;
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u32 trace_dma_idx;
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bool secure_mode;
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bool raise_priv_sec;
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struct {
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u32 dma_base;
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u16 dma_base1;
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u8 dma_offset;
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u16 fb_size;
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u8 dma_idx;
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} gc6_ctx;
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u8 pad;
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};
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#define NV_PMU_UNIT_INIT 0x07
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#define NV_PMU_UNIT_ACR 0x0a
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struct nv_pmu_init_msg {
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struct nvfw_falcon_msg hdr;
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#define NV_PMU_INIT_MSG_INIT 0x00
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u8 msg_type;
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u8 pad;
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u16 os_debug_entry_point;
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struct {
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u16 size;
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u16 offset;
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u8 index;
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u8 pad;
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} queue_info[5];
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u16 sw_managed_area_offset;
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u16 sw_managed_area_size;
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};
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struct nv_pmu_acr_cmd {
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struct nvfw_falcon_cmd hdr;
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#define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00
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#define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON 0x01
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#define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS 0x03
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u8 cmd_type;
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};
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struct nv_pmu_acr_msg {
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struct nvfw_falcon_cmd hdr;
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u8 msg_type;
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};
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struct nv_pmu_acr_init_wpr_region_cmd {
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struct nv_pmu_acr_cmd cmd;
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u32 region_id;
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u32 wpr_offset;
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};
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struct nv_pmu_acr_init_wpr_region_msg {
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struct nv_pmu_acr_msg msg;
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u32 error_code;
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};
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struct nv_pmu_acr_bootstrap_falcon_cmd {
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struct nv_pmu_acr_cmd cmd;
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#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
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#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
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u32 flags;
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u32 falcon_id;
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};
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struct nv_pmu_acr_bootstrap_falcon_msg {
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struct nv_pmu_acr_msg msg;
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u32 falcon_id;
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};
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struct nv_pmu_acr_bootstrap_multiple_falcons_cmd {
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struct nv_pmu_acr_cmd cmd;
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#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES 0x00000000
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#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_NO 0x00000001
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u32 flags;
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u32 falcon_mask;
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u32 use_va_mask;
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u32 wpr_lo;
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u32 wpr_hi;
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};
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struct nv_pmu_acr_bootstrap_multiple_falcons_msg {
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struct nv_pmu_acr_msg msg;
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u32 falcon_mask;
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};
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#endif
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