333 lines
8.9 KiB
C
333 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_top.h"
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#include "dpu_kms.h"
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#define SSPP_SPARE 0x28
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#define FLD_SPLIT_DISPLAY_CMD BIT(1)
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#define FLD_SMART_PANEL_FREE_RUN BIT(2)
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#define FLD_INTF_1_SW_TRG_MUX BIT(4)
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#define FLD_INTF_2_SW_TRG_MUX BIT(8)
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#define FLD_TE_LINE_INTER_WATERLEVEL_MASK 0xFFFF
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#define DANGER_STATUS 0x360
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#define SAFE_STATUS 0x364
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#define TE_LINE_INTERVAL 0x3F4
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#define TRAFFIC_SHAPER_EN BIT(31)
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#define TRAFFIC_SHAPER_RD_CLIENT(num) (0x030 + (num * 4))
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#define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4))
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#define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4
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#define MDP_WD_TIMER_0_CTL 0x380
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#define MDP_WD_TIMER_0_CTL2 0x384
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#define MDP_WD_TIMER_0_LOAD_VALUE 0x388
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#define MDP_WD_TIMER_1_CTL 0x390
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#define MDP_WD_TIMER_1_CTL2 0x394
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#define MDP_WD_TIMER_1_LOAD_VALUE 0x398
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#define MDP_WD_TIMER_2_CTL 0x420
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#define MDP_WD_TIMER_2_CTL2 0x424
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#define MDP_WD_TIMER_2_LOAD_VALUE 0x428
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#define MDP_WD_TIMER_3_CTL 0x430
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#define MDP_WD_TIMER_3_CTL2 0x434
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#define MDP_WD_TIMER_3_LOAD_VALUE 0x438
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#define MDP_WD_TIMER_4_CTL 0x440
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#define MDP_WD_TIMER_4_CTL2 0x444
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#define MDP_WD_TIMER_4_LOAD_VALUE 0x448
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#define MDP_TICK_COUNT 16
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#define XO_CLK_RATE 19200
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#define MS_TICKS_IN_SEC 1000
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#define CALCULATE_WD_LOAD_VALUE(fps) \
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((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps)))
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#define DCE_SEL 0x450
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static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
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struct split_pipe_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 upper_pipe = 0;
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u32 lower_pipe = 0;
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if (!mdp || !cfg)
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return;
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c = &mdp->hw;
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if (cfg->en) {
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if (cfg->mode == INTF_MODE_CMD) {
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lower_pipe = FLD_SPLIT_DISPLAY_CMD;
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/* interface controlling sw trigger */
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if (cfg->intf == INTF_2)
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lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
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else
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lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
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upper_pipe = lower_pipe;
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} else {
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if (cfg->intf == INTF_2) {
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lower_pipe = FLD_INTF_1_SW_TRG_MUX;
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upper_pipe = FLD_INTF_2_SW_TRG_MUX;
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} else {
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lower_pipe = FLD_INTF_2_SW_TRG_MUX;
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upper_pipe = FLD_INTF_1_SW_TRG_MUX;
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}
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}
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}
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DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
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DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe);
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DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe);
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DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
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}
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static bool dpu_hw_setup_clk_force_ctrl(struct dpu_hw_mdp *mdp,
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enum dpu_clk_ctrl_type clk_ctrl, bool enable)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 reg_off, bit_off;
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u32 reg_val, new_val;
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bool clk_forced_on;
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if (!mdp)
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return false;
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c = &mdp->hw;
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if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX)
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return false;
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reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off;
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bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off;
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reg_val = DPU_REG_READ(c, reg_off);
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if (enable)
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new_val = reg_val | BIT(bit_off);
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else
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new_val = reg_val & ~BIT(bit_off);
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DPU_REG_WRITE(c, reg_off, new_val);
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clk_forced_on = !(reg_val & BIT(bit_off));
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return clk_forced_on;
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}
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static void dpu_hw_get_danger_status(struct dpu_hw_mdp *mdp,
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struct dpu_danger_safe_status *status)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 value;
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if (!mdp || !status)
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return;
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c = &mdp->hw;
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value = DPU_REG_READ(c, DANGER_STATUS);
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status->mdp = (value >> 0) & 0x3;
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status->sspp[SSPP_VIG0] = (value >> 4) & 0x3;
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status->sspp[SSPP_VIG1] = (value >> 6) & 0x3;
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status->sspp[SSPP_VIG2] = (value >> 8) & 0x3;
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status->sspp[SSPP_VIG3] = (value >> 10) & 0x3;
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status->sspp[SSPP_RGB0] = (value >> 12) & 0x3;
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status->sspp[SSPP_RGB1] = (value >> 14) & 0x3;
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status->sspp[SSPP_RGB2] = (value >> 16) & 0x3;
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status->sspp[SSPP_RGB3] = (value >> 18) & 0x3;
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status->sspp[SSPP_DMA0] = (value >> 20) & 0x3;
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status->sspp[SSPP_DMA1] = (value >> 22) & 0x3;
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status->sspp[SSPP_DMA2] = (value >> 28) & 0x3;
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status->sspp[SSPP_DMA3] = (value >> 30) & 0x3;
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status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x3;
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status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x3;
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}
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static void dpu_hw_setup_vsync_source(struct dpu_hw_mdp *mdp,
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struct dpu_vsync_source_cfg *cfg)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 reg, wd_load_value, wd_ctl, wd_ctl2, i;
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static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};
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if (!mdp || !cfg || (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
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return;
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c = &mdp->hw;
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reg = DPU_REG_READ(c, MDP_VSYNC_SEL);
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for (i = 0; i < cfg->pp_count; i++) {
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int pp_idx = cfg->ppnumber[i] - PINGPONG_0;
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if (pp_idx >= ARRAY_SIZE(pp_offset))
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continue;
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reg &= ~(0xf << pp_offset[pp_idx]);
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reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
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}
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DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg);
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if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
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cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) {
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switch (cfg->vsync_source) {
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case DPU_VSYNC_SOURCE_WD_TIMER_4:
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wd_load_value = MDP_WD_TIMER_4_LOAD_VALUE;
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wd_ctl = MDP_WD_TIMER_4_CTL;
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wd_ctl2 = MDP_WD_TIMER_4_CTL2;
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break;
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case DPU_VSYNC_SOURCE_WD_TIMER_3:
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wd_load_value = MDP_WD_TIMER_3_LOAD_VALUE;
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wd_ctl = MDP_WD_TIMER_3_CTL;
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wd_ctl2 = MDP_WD_TIMER_3_CTL2;
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break;
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case DPU_VSYNC_SOURCE_WD_TIMER_2:
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wd_load_value = MDP_WD_TIMER_2_LOAD_VALUE;
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wd_ctl = MDP_WD_TIMER_2_CTL;
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wd_ctl2 = MDP_WD_TIMER_2_CTL2;
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break;
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case DPU_VSYNC_SOURCE_WD_TIMER_1:
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wd_load_value = MDP_WD_TIMER_1_LOAD_VALUE;
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wd_ctl = MDP_WD_TIMER_1_CTL;
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wd_ctl2 = MDP_WD_TIMER_1_CTL2;
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break;
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case DPU_VSYNC_SOURCE_WD_TIMER_0:
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default:
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wd_load_value = MDP_WD_TIMER_0_LOAD_VALUE;
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wd_ctl = MDP_WD_TIMER_0_CTL;
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wd_ctl2 = MDP_WD_TIMER_0_CTL2;
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break;
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}
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DPU_REG_WRITE(c, wd_load_value,
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CALCULATE_WD_LOAD_VALUE(cfg->frame_rate));
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DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */
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reg = DPU_REG_READ(c, wd_ctl2);
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reg |= BIT(8); /* enable heartbeat timer */
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reg |= BIT(0); /* enable WD timer */
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DPU_REG_WRITE(c, wd_ctl2, reg);
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/* make sure that timers are enabled/disabled for vsync state */
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wmb();
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}
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}
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static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
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struct dpu_danger_safe_status *status)
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{
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struct dpu_hw_blk_reg_map *c;
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u32 value;
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if (!mdp || !status)
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return;
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c = &mdp->hw;
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value = DPU_REG_READ(c, SAFE_STATUS);
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status->mdp = (value >> 0) & 0x1;
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status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
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status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
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status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
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status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
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status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
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status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
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status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
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status->sspp[SSPP_RGB3] = (value >> 18) & 0x1;
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status->sspp[SSPP_DMA0] = (value >> 20) & 0x1;
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status->sspp[SSPP_DMA1] = (value >> 22) & 0x1;
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status->sspp[SSPP_DMA2] = (value >> 28) & 0x1;
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status->sspp[SSPP_DMA3] = (value >> 30) & 0x1;
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status->sspp[SSPP_CURSOR0] = (value >> 24) & 0x1;
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status->sspp[SSPP_CURSOR1] = (value >> 26) & 0x1;
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}
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static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
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{
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struct dpu_hw_blk_reg_map *c;
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if (!mdp)
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return;
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c = &mdp->hw;
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DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
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}
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static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
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unsigned long cap)
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{
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ops->setup_split_pipe = dpu_hw_setup_split_pipe;
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ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
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ops->get_danger_status = dpu_hw_get_danger_status;
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ops->setup_vsync_source = dpu_hw_setup_vsync_source;
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ops->get_safe_status = dpu_hw_get_safe_status;
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ops->intf_audio_select = dpu_hw_intf_audio_select;
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}
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static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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if (!m || !addr || !b)
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return ERR_PTR(-EINVAL);
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for (i = 0; i < m->mdp_count; i++) {
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if (mdp == m->mdp[i].id) {
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b->base_off = addr;
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b->blk_off = m->mdp[i].base;
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b->length = m->mdp[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = DPU_DBG_MASK_TOP;
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return &m->mdp[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_mdp *mdp;
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const struct dpu_mdp_cfg *cfg;
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if (!addr || !m)
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return ERR_PTR(-EINVAL);
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mdp = kzalloc(sizeof(*mdp), GFP_KERNEL);
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if (!mdp)
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return ERR_PTR(-ENOMEM);
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cfg = _top_offset(idx, m, addr, &mdp->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(mdp);
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return ERR_PTR(-EINVAL);
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}
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/*
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* Assign ops
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*/
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mdp->idx = idx;
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mdp->caps = cfg;
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_setup_mdp_ops(&mdp->ops, mdp->caps->features);
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return mdp;
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}
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void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp)
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{
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kfree(mdp);
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}
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