376 lines
11 KiB
C
376 lines
11 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2019 Intel Corporation
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*/
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#ifndef _INTEL_GUC_FWIF_H
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#define _INTEL_GUC_FWIF_H
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#include <linux/bits.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include "gt/intel_engine_types.h"
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#include "abi/guc_actions_abi.h"
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#include "abi/guc_actions_slpc_abi.h"
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#include "abi/guc_errors_abi.h"
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#include "abi/guc_communication_mmio_abi.h"
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#include "abi/guc_communication_ctb_abi.h"
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#include "abi/guc_messages_abi.h"
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/* Payload length only i.e. don't include G2H header length */
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#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2
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#define G2H_LEN_DW_DEREGISTER_CONTEXT 1
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#define GUC_CONTEXT_DISABLE 0
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#define GUC_CONTEXT_ENABLE 1
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#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
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#define GUC_CLIENT_PRIORITY_HIGH 1
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#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
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#define GUC_CLIENT_PRIORITY_NORMAL 3
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#define GUC_CLIENT_PRIORITY_NUM 4
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#define GUC_MAX_LRC_DESCRIPTORS 65535
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#define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
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#define GUC_RENDER_ENGINE 0
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#define GUC_VIDEO_ENGINE 1
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#define GUC_BLITTER_ENGINE 2
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#define GUC_VIDEOENHANCE_ENGINE 3
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#define GUC_VIDEO_ENGINE2 4
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#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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#define GUC_RENDER_CLASS 0
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#define GUC_VIDEO_CLASS 1
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#define GUC_VIDEOENHANCE_CLASS 2
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#define GUC_BLITTER_CLASS 3
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#define GUC_RESERVED_CLASS 4
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#define GUC_LAST_ENGINE_CLASS GUC_RESERVED_CLASS
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#define GUC_MAX_ENGINE_CLASSES 16
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#define GUC_MAX_INSTANCES_PER_CLASS 32
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#define GUC_DOORBELL_INVALID 256
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#define GUC_WQ_SIZE (PAGE_SIZE * 2)
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/* Work queue item header definitions */
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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#define WQ_STATUS_CMD_ERROR 3
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#define WQ_STATUS_ENGINE_ID_NOT_USED 4
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#define WQ_STATUS_SUSPENDED_FROM_RESET 5
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#define WQ_TYPE_SHIFT 0
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#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
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#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
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#define WQ_TARGET_SHIFT 10
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#define WQ_LEN_SHIFT 16
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#define WQ_NO_WCFLUSH_WAIT (1 << 27)
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#define WQ_PRESENT_WORKLOAD (1 << 28)
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#define WQ_RING_TAIL_SHIFT 20
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#define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */
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#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
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#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
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#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
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#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
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#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
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#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
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#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
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#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
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#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
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#define GUC_CTL_LOG_PARAMS 0
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#define GUC_LOG_VALID (1 << 0)
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#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
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#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
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#define GUC_LOG_CRASH_SHIFT 4
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#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
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#define GUC_LOG_DEBUG_SHIFT 6
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#define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
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#define GUC_LOG_BUF_ADDR_SHIFT 12
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#define GUC_CTL_WA 1
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#define GUC_CTL_FEATURE 2
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#define GUC_CTL_DISABLE_SCHEDULER (1 << 14)
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#define GUC_CTL_ENABLE_SLPC BIT(2)
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#define GUC_CTL_DEBUG 3
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#define GUC_LOG_VERBOSITY_SHIFT 0
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#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
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/* Verbosity range-check limits, without the shift */
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#define GUC_LOG_VERBOSITY_MIN 0
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#define GUC_LOG_VERBOSITY_MAX 3
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#define GUC_LOG_VERBOSITY_MASK 0x0000000f
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#define GUC_LOG_DESTINATION_MASK (3 << 4)
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#define GUC_LOG_DISABLED (1 << 6)
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#define GUC_PROFILE_ENABLED (1 << 7)
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#define GUC_CTL_ADS 4
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#define GUC_ADS_ADDR_SHIFT 1
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#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
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#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
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/* Generic GT SysInfo data types */
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#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
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#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
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#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
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#define GUC_GENERIC_GT_SYSINFO_MAX 16
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/*
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* The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6].
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* Bit 7 can be used for operations that apply to all engine classes&instances.
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*/
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#define GUC_ENGINE_CLASS_SHIFT 0
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#define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT)
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#define GUC_ENGINE_INSTANCE_SHIFT 3
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#define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT)
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#define GUC_ENGINE_ALL_INSTANCES BIT(7)
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#define MAKE_GUC_ID(class, instance) \
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(((class) << GUC_ENGINE_CLASS_SHIFT) | \
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((instance) << GUC_ENGINE_INSTANCE_SHIFT))
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#define GUC_ID_TO_ENGINE_CLASS(guc_id) \
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(((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
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#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
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(((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
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#define SLPC_EVENT(id, c) (\
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FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
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FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \
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)
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static inline u8 engine_class_to_guc_class(u8 class)
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{
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BUILD_BUG_ON(GUC_RENDER_CLASS != RENDER_CLASS);
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BUILD_BUG_ON(GUC_BLITTER_CLASS != COPY_ENGINE_CLASS);
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BUILD_BUG_ON(GUC_VIDEO_CLASS != VIDEO_DECODE_CLASS);
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BUILD_BUG_ON(GUC_VIDEOENHANCE_CLASS != VIDEO_ENHANCEMENT_CLASS);
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GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
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return class;
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}
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static inline u8 guc_class_to_engine_class(u8 guc_class)
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{
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GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
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GEM_BUG_ON(guc_class == GUC_RESERVED_CLASS);
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return guc_class;
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}
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/* Work item for submitting workloads into work queue of GuC. */
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struct guc_wq_item {
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u32 header;
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u32 context_desc;
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u32 submit_element_info;
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u32 fence_id;
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} __packed;
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struct guc_process_desc {
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u32 stage_id;
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u64 db_base_addr;
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u32 head;
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u32 tail;
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u32 error_offset;
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u64 wq_base_addr;
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u32 wq_size_bytes;
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u32 wq_status;
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u32 engine_presence;
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u32 priority;
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u32 reserved[30];
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} __packed;
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#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
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#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
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#define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 500000
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/* Preempt to idle on quantum expiry */
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#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
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/*
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* GuC Context registration descriptor.
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* FIXME: This is only required to exist during context registration.
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* The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
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* is not required.
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*/
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struct guc_lrc_desc {
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u32 hw_context_desc;
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u32 slpm_perf_mode_hint; /* SPLC v1 only */
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u32 slpm_freq_hint;
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u32 engine_submit_mask; /* In logical space */
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u8 engine_class;
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u8 reserved0[3];
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u32 priority;
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u32 process_desc;
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u32 wq_addr;
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u32 wq_size;
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u32 context_flags; /* CONTEXT_REGISTRATION_* */
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/* Time for one workload to execute. (in micro seconds) */
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u32 execution_quantum;
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/* Time to wait for a preemption request to complete before issuing a
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* reset. (in micro seconds).
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*/
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u32 preemption_timeout;
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u32 policy_flags; /* CONTEXT_POLICY_* */
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u32 reserved1[19];
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} __packed;
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#define GUC_POWER_UNSPECIFIED 0
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#define GUC_POWER_D0 1
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#define GUC_POWER_D1 2
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#define GUC_POWER_D2 3
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#define GUC_POWER_D3 4
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/* Scheduling policy settings */
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#define GLOBAL_POLICY_MAX_NUM_WI 15
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/* Don't reset an engine upon preemption failure */
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#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
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#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
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struct guc_policies {
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u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
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/* In micro seconds. How much time to allow before DPC processing is
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* called back via interrupt (to prevent DPC queue drain starving).
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* Typically 1000s of micro seconds (example only, not granularity). */
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u32 dpc_promote_time;
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/* Must be set to take these new values. */
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u32 is_valid;
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/* Max number of WIs to process per call. A large value may keep CS
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* idle. */
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u32 max_num_work_items;
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u32 global_flags;
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u32 reserved[4];
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} __packed;
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/* GuC MMIO reg state struct */
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struct guc_mmio_reg {
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u32 offset;
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u32 value;
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u32 flags;
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#define GUC_REGSET_MASKED (1 << 0)
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} __packed;
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/* GuC register sets */
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struct guc_mmio_reg_set {
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u32 address;
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u16 count;
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u16 reserved;
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} __packed;
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/* HW info */
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struct guc_gt_system_info {
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u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
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u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
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} __packed;
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/* GuC Additional Data Struct */
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struct guc_ads {
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struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 reserved0;
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u32 scheduler_policies;
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u32 gt_system_info;
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u32 reserved1;
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u32 control_data;
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u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
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u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
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u32 private_data;
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u32 reserved[15];
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} __packed;
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/* GuC logging structures */
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enum guc_log_buffer_type {
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GUC_DEBUG_LOG_BUFFER,
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GUC_CRASH_DUMP_LOG_BUFFER,
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GUC_MAX_LOG_BUFFER
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};
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/**
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* struct guc_log_buffer_state - GuC log buffer state
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*
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* Below state structure is used for coordination of retrieval of GuC firmware
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* logs. Separate state is maintained for each log buffer type.
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* read_ptr points to the location where i915 read last in log buffer and
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* is read only for GuC firmware. write_ptr is incremented by GuC with number
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* of bytes written for each log entry and is read only for i915.
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* When any type of log buffer becomes half full, GuC sends a flush interrupt.
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* GuC firmware expects that while it is writing to 2nd half of the buffer,
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* first half would get consumed by Host and then get a flush completed
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* acknowledgment from Host, so that it does not end up doing any overwrite
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* causing loss of logs. So when buffer gets half filled & i915 has requested
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* for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
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* to the value of write_ptr and raise the interrupt.
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* On receiving the interrupt i915 should read the buffer, clear flush_to_file
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* field and also update read_ptr with the value of sample_write_ptr, before
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* sending an acknowledgment to GuC. marker & version fields are for internal
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* usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
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* time GuC detects the log buffer overflow.
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*/
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struct guc_log_buffer_state {
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u32 marker[2];
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u32 read_ptr;
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u32 write_ptr;
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u32 size;
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u32 sampled_write_ptr;
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union {
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struct {
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u32 flush_to_file:1;
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u32 buffer_full_cnt:4;
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u32 reserved:27;
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};
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u32 flags;
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};
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u32 version;
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} __packed;
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struct guc_ctx_report {
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u32 report_return_status;
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u32 reserved1[64];
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u32 affected_count;
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u32 reserved2[2];
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} __packed;
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/* GuC Shared Context Data Struct */
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struct guc_shared_ctx_data {
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u32 addr_of_last_preempted_data_low;
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u32 addr_of_last_preempted_data_high;
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u32 addr_of_last_preempted_data_high_tmp;
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u32 padding;
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u32 is_mapped_to_proxy;
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u32 proxy_ctx_id;
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u32 engine_reset_ctx_id;
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u32 media_reset_count;
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u32 reserved1[8];
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u32 uk_last_ctx_switch_reason;
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u32 was_reset;
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u32 lrca_gpu_addr;
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u64 execlist_ctx;
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u32 reserved2[66];
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struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
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} __packed;
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/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
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enum intel_guc_recv_message {
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INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
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INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
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};
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#endif
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