772 lines
20 KiB
C
772 lines
20 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "dm_services.h"
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#include "basics/conversion.h"
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#include "dce_opp.h"
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#include "reg_helper.h"
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#define REG(reg)\
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(opp110->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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opp110->opp_shift->field_name, opp110->opp_mask->field_name
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#define CTX \
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opp110->base.ctx
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enum {
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MAX_PWL_ENTRY = 128,
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MAX_REGIONS_NUMBER = 16
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};
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enum {
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MAX_LUT_ENTRY = 256,
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MAX_NUMBER_OF_ENTRIES = 256
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};
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enum {
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OUTPUT_CSC_MATRIX_SIZE = 12
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};
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/*
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*****************************************************************************
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* Function: regamma_config_regions_and_segments
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*
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* build regamma curve by using predefined hw points
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* uses interface parameters ,like EDID coeff.
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*
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* @param : parameters interface parameters
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* @return void
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*
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* @note
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*
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* @see
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*
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*****************************************************************************
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*/
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/*
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* set_truncation
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* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
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* 2) enable truncation
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* 3) HW remove 12bit FMT support for DCE11 power saving reason.
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*/
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static void set_truncation(
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struct dce110_opp *opp110,
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const struct bit_depth_reduction_params *params)
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{
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/*Disable truncation*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 0,
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FMT_TRUNCATE_DEPTH, 0,
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FMT_TRUNCATE_MODE, 0);
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if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
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/* 8bpc trunc on YCbCr422*/
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if (params->flags.TRUNCATE_DEPTH == 1)
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH, 1,
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FMT_TRUNCATE_MODE, 0);
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else if (params->flags.TRUNCATE_DEPTH == 2)
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/* 10bpc trunc on YCbCr422*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH, 2,
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FMT_TRUNCATE_MODE, 0);
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return;
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}
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/* on other format-to do */
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if (params->flags.TRUNCATE_ENABLED == 0)
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return;
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/*Set truncation depth and Enable truncation*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH,
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params->flags.TRUNCATE_DEPTH,
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FMT_TRUNCATE_MODE,
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params->flags.TRUNCATE_MODE);
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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/*
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* dce60_set_truncation
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* 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
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* 2) enable truncation
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* 3) HW remove 12bit FMT support for DCE11 power saving reason.
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*/
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static void dce60_set_truncation(
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struct dce110_opp *opp110,
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const struct bit_depth_reduction_params *params)
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{
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/* DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL reg */
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/*Disable truncation*/
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REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 0,
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FMT_TRUNCATE_DEPTH, 0);
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if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
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/* 8bpc trunc on YCbCr422*/
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if (params->flags.TRUNCATE_DEPTH == 1)
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REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH, 1);
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else if (params->flags.TRUNCATE_DEPTH == 2)
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/* 10bpc trunc on YCbCr422*/
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REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH, 2);
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return;
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}
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/* on other format-to do */
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if (params->flags.TRUNCATE_ENABLED == 0)
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return;
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/*Set truncation depth and Enable truncation*/
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REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
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FMT_TRUNCATE_EN, 1,
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FMT_TRUNCATE_DEPTH,
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params->flags.TRUNCATE_DEPTH);
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}
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#endif
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/*
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* set_spatial_dither
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* 1) set spatial dithering mode: pattern of seed
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* 2) set spatial dithering depth: 0 for 18bpp or 1 for 24bpp
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* 3) set random seed
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* 4) set random mode
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* lfsr is reset every frame or not reset
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* RGB dithering method
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* 0: RGB data are all dithered with x^28+x^3+1
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* 1: R data is dithered with x^28+x^3+1
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* G data is dithered with x^28+X^9+1
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* B data is dithered with x^28+x^13+1
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* enable high pass filter or not
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* 5) enable spatical dithering
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*/
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static void set_spatial_dither(
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struct dce110_opp *opp110,
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const struct bit_depth_reduction_params *params)
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{
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/*Disable spatial (random) dithering*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_SPATIAL_DITHER_EN, 0,
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FMT_SPATIAL_DITHER_DEPTH, 0,
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FMT_SPATIAL_DITHER_MODE, 0);
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_HIGHPASS_RANDOM_ENABLE, 0,
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FMT_FRAME_RANDOM_ENABLE, 0,
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FMT_RGB_RANDOM_ENABLE, 0);
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REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_DITHER_EN, 0);
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if (params->flags.SPATIAL_DITHER_ENABLED == 0)
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return;
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/* only use FRAME_COUNTER_MAX if frameRandom == 1*/
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if (opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX &&
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opp110->opp_mask->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP) {
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if (params->flags.FRAME_RANDOM == 1) {
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if (params->flags.SPATIAL_DITHER_DEPTH == 0 ||
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params->flags.SPATIAL_DITHER_DEPTH == 1) {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
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} else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
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} else
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return;
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} else {
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REG_UPDATE_2(FMT_CONTROL,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
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FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
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}
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}
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/* Set seed for random values for
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* spatial dithering for R,G,B channels
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*/
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REG_UPDATE(FMT_DITHER_RAND_R_SEED,
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FMT_RAND_R_SEED, params->r_seed_value);
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REG_UPDATE(FMT_DITHER_RAND_G_SEED,
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FMT_RAND_G_SEED, params->g_seed_value);
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REG_UPDATE(FMT_DITHER_RAND_B_SEED,
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FMT_RAND_B_SEED, params->b_seed_value);
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/* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
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* offset for the R/Cr channel, lower 4LSB
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* is forced to zeros. Typically set to 0
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* RGB and 0x80000 YCbCr.
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*/
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/* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
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* offset for the G/Y channel, lower 4LSB is
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* forced to zeros. Typically set to 0 RGB
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* and 0x80000 YCbCr.
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*/
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/* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
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* offset for the B/Cb channel, lower 4LSB is
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* forced to zeros. Typically set to 0 RGB and
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* 0x80000 YCbCr.
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*/
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/* Disable High pass filter
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* Reset only at startup
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* Set RGB data dithered with x^28+x^3+1
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*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
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FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
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FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
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/* Set spatial dithering bit depth
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* Set spatial dithering mode
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* (default is Seed patterrn AAAA...)
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* Enable spatial dithering
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*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
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FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
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FMT_SPATIAL_DITHER_EN, 1);
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}
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/*
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* SetTemporalDither (Frame Modulation)
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* 1) set temporal dither depth
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* 2) select pattern: from hard-coded pattern or programmable pattern
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* 3) select optimized strips for BGR or RGB LCD sub-pixel
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* 4) set s matrix
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* 5) set t matrix
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* 6) set grey level for 0.25, 0.5, 0.75
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* 7) enable temporal dithering
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*/
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static void set_temporal_dither(
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struct dce110_opp *opp110,
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const struct bit_depth_reduction_params *params)
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{
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/*Disable temporal (frame modulation) dithering first*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_DITHER_EN, 0,
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FMT_TEMPORAL_DITHER_RESET, 0,
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FMT_TEMPORAL_DITHER_OFFSET, 0);
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REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_DITHER_DEPTH, 0,
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FMT_TEMPORAL_LEVEL, 0);
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_25FRC_SEL, 0,
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FMT_50FRC_SEL, 0,
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FMT_75FRC_SEL, 0);
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/* no 10bpc dither on DCE11*/
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if (params->flags.FRAME_MODULATION_ENABLED == 0 ||
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params->flags.FRAME_MODULATION_DEPTH == 2)
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return;
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/* Set temporal dithering depth*/
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_DITHER_DEPTH, params->flags.FRAME_MODULATION_DEPTH,
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FMT_TEMPORAL_DITHER_RESET, 0,
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FMT_TEMPORAL_DITHER_OFFSET, 0);
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/*Select legacy pattern based on FRC and Temporal level*/
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if (REG(FMT_TEMPORAL_DITHER_PATTERN_CONTROL)) {
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REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
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/*Set s matrix*/
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REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
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/*Set t matrix*/
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REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
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}
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/*Select patterns for 0.25, 0.5 and 0.75 grey level*/
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REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_LEVEL, params->flags.TEMPORAL_LEVEL);
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REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
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FMT_25FRC_SEL, params->flags.FRC25,
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FMT_50FRC_SEL, params->flags.FRC50,
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FMT_75FRC_SEL, params->flags.FRC75);
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/*Enable bit reduction by temporal (frame modulation) dithering*/
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REG_UPDATE(FMT_BIT_DEPTH_CONTROL,
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FMT_TEMPORAL_DITHER_EN, 1);
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}
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/*
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* Set Clamping
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* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
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* 1 for 8 bpc
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* 2 for 10 bpc
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* 3 for 12 bpc
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* 7 for programable
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* 2) Enable clamp if Limited range requested
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*/
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void dce110_opp_set_clamping(
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struct dce110_opp *opp110,
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const struct clamping_and_pixel_encoding_params *params)
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{
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 0,
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FMT_CLAMP_COLOR_FORMAT, 0);
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switch (params->clamping_level) {
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case CLAMPING_FULL_RANGE:
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break;
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case CLAMPING_LIMITED_RANGE_8BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 1);
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break;
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case CLAMPING_LIMITED_RANGE_10BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 2);
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break;
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case CLAMPING_LIMITED_RANGE_12BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 3);
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break;
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case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
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/*Set clamp control*/
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 7);
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/*set the defaults*/
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REG_SET_2(FMT_CLAMP_COMPONENT_R, 0,
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FMT_CLAMP_LOWER_R, 0x10,
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FMT_CLAMP_UPPER_R, 0xFEF);
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REG_SET_2(FMT_CLAMP_COMPONENT_G, 0,
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FMT_CLAMP_LOWER_G, 0x10,
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FMT_CLAMP_UPPER_G, 0xFEF);
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REG_SET_2(FMT_CLAMP_COMPONENT_B, 0,
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FMT_CLAMP_LOWER_B, 0x10,
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FMT_CLAMP_UPPER_B, 0xFEF);
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break;
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default:
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break;
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}
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}
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#if defined(CONFIG_DRM_AMD_DC_SI)
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/*
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* Set Clamping for DCE6 parts
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* 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
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* 1 for 8 bpc
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* 2 for 10 bpc
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* 3 for 12 bpc
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* 7 for programable
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* 2) Enable clamp if Limited range requested
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*/
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static void dce60_opp_set_clamping(
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struct dce110_opp *opp110,
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const struct clamping_and_pixel_encoding_params *params)
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{
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 0,
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FMT_CLAMP_COLOR_FORMAT, 0);
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switch (params->clamping_level) {
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case CLAMPING_FULL_RANGE:
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break;
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case CLAMPING_LIMITED_RANGE_8BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 1);
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break;
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case CLAMPING_LIMITED_RANGE_10BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 2);
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break;
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case CLAMPING_LIMITED_RANGE_12BPC:
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 3);
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break;
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case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
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/*Set clamp control*/
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REG_SET_2(FMT_CLAMP_CNTL, 0,
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FMT_CLAMP_DATA_EN, 1,
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FMT_CLAMP_COLOR_FORMAT, 7);
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/* DCE6 does have FMT_CLAMP_COMPONENT_{R,G,B} registers */
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break;
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default:
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break;
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}
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}
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#endif
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/*
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* set_pixel_encoding
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*
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* Set Pixel Encoding
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* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
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* 1: YCbCr 4:2:2
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*/
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static void set_pixel_encoding(
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struct dce110_opp *opp110,
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const struct clamping_and_pixel_encoding_params *params)
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{
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if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS)
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REG_UPDATE_3(FMT_CONTROL,
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FMT_PIXEL_ENCODING, 0,
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FMT_SUBSAMPLING_MODE, 0,
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FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
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else
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REG_UPDATE_2(FMT_CONTROL,
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FMT_PIXEL_ENCODING, 0,
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FMT_SUBSAMPLING_MODE, 0);
|
|
|
|
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
|
|
REG_UPDATE_2(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 1,
|
|
FMT_SUBSAMPLING_ORDER, 0);
|
|
}
|
|
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
|
|
REG_UPDATE_3(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 2,
|
|
FMT_SUBSAMPLING_MODE, 2,
|
|
FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
|
|
}
|
|
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
/*
|
|
* dce60_set_pixel_encoding
|
|
* DCE6 has no FMT_SUBSAMPLING_{MODE,ORDER} bits in FMT_CONTROL reg
|
|
* Set Pixel Encoding
|
|
* 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
|
|
* 1: YCbCr 4:2:2
|
|
*/
|
|
static void dce60_set_pixel_encoding(
|
|
struct dce110_opp *opp110,
|
|
const struct clamping_and_pixel_encoding_params *params)
|
|
{
|
|
if (opp110->opp_mask->FMT_CBCR_BIT_REDUCTION_BYPASS)
|
|
REG_UPDATE_2(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 0,
|
|
FMT_CBCR_BIT_REDUCTION_BYPASS, 0);
|
|
else
|
|
REG_UPDATE(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 0);
|
|
|
|
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
|
|
REG_UPDATE(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 1);
|
|
}
|
|
if (params->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
|
|
REG_UPDATE_2(FMT_CONTROL,
|
|
FMT_PIXEL_ENCODING, 2,
|
|
FMT_CBCR_BIT_REDUCTION_BYPASS, 1);
|
|
}
|
|
|
|
}
|
|
#endif
|
|
|
|
void dce110_opp_program_bit_depth_reduction(
|
|
struct output_pixel_processor *opp,
|
|
const struct bit_depth_reduction_params *params)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
set_truncation(opp110, params);
|
|
set_spatial_dither(opp110, params);
|
|
set_temporal_dither(opp110, params);
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static void dce60_opp_program_bit_depth_reduction(
|
|
struct output_pixel_processor *opp,
|
|
const struct bit_depth_reduction_params *params)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
dce60_set_truncation(opp110, params);
|
|
set_spatial_dither(opp110, params);
|
|
set_temporal_dither(opp110, params);
|
|
}
|
|
#endif
|
|
|
|
void dce110_opp_program_clamping_and_pixel_encoding(
|
|
struct output_pixel_processor *opp,
|
|
const struct clamping_and_pixel_encoding_params *params)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
dce110_opp_set_clamping(opp110, params);
|
|
set_pixel_encoding(opp110, params);
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static void dce60_opp_program_clamping_and_pixel_encoding(
|
|
struct output_pixel_processor *opp,
|
|
const struct clamping_and_pixel_encoding_params *params)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
dce60_opp_set_clamping(opp110, params);
|
|
dce60_set_pixel_encoding(opp110, params);
|
|
}
|
|
#endif
|
|
|
|
|
|
static void program_formatter_420_memory(struct output_pixel_processor *opp)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
uint32_t fmt_mem_cntl_value;
|
|
|
|
/* Program source select*/
|
|
/* Use HW default source select for FMT_MEMORYx_CONTROL */
|
|
/* Use that value for FMT_SRC_SELECT as well*/
|
|
REG_GET(CONTROL,
|
|
FMT420_MEM0_SOURCE_SEL, &fmt_mem_cntl_value);
|
|
|
|
REG_UPDATE(FMT_CONTROL,
|
|
FMT_SRC_SELECT, fmt_mem_cntl_value);
|
|
|
|
/* Turn on the memory */
|
|
REG_UPDATE(CONTROL,
|
|
FMT420_MEM0_PWR_FORCE, 0);
|
|
}
|
|
|
|
void dce110_opp_set_dyn_expansion(
|
|
struct output_pixel_processor *opp,
|
|
enum dc_color_space color_sp,
|
|
enum dc_color_depth color_dpth,
|
|
enum signal_type signal)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
|
|
FMT_DYNAMIC_EXP_EN, 0,
|
|
FMT_DYNAMIC_EXP_MODE, 0);
|
|
|
|
/*00 - 10-bit -> 12-bit dynamic expansion*/
|
|
/*01 - 8-bit -> 12-bit dynamic expansion*/
|
|
if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
|
|
signal == SIGNAL_TYPE_DISPLAY_PORT ||
|
|
signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
|
|
switch (color_dpth) {
|
|
case COLOR_DEPTH_888:
|
|
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
|
|
FMT_DYNAMIC_EXP_EN, 1,
|
|
FMT_DYNAMIC_EXP_MODE, 1);
|
|
break;
|
|
case COLOR_DEPTH_101010:
|
|
REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
|
|
FMT_DYNAMIC_EXP_EN, 1,
|
|
FMT_DYNAMIC_EXP_MODE, 0);
|
|
break;
|
|
case COLOR_DEPTH_121212:
|
|
REG_UPDATE_2(
|
|
FMT_DYNAMIC_EXP_CNTL,
|
|
FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
|
|
FMT_DYNAMIC_EXP_MODE, 0);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void program_formatter_reset_dig_resync_fifo(struct output_pixel_processor *opp)
|
|
{
|
|
struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
|
|
|
|
/* clear previous phase lock status*/
|
|
REG_UPDATE(FMT_CONTROL,
|
|
FMT_420_PIXEL_PHASE_LOCKED_CLEAR, 1);
|
|
|
|
/* poll until FMT_420_PIXEL_PHASE_LOCKED become 1*/
|
|
REG_WAIT(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, 1, 10, 10);
|
|
|
|
}
|
|
|
|
void dce110_opp_program_fmt(
|
|
struct output_pixel_processor *opp,
|
|
struct bit_depth_reduction_params *fmt_bit_depth,
|
|
struct clamping_and_pixel_encoding_params *clamping)
|
|
{
|
|
/* dithering is affected by <CrtcSourceSelect>, hence should be
|
|
* programmed afterwards */
|
|
|
|
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
|
program_formatter_420_memory(opp);
|
|
|
|
dce110_opp_program_bit_depth_reduction(
|
|
opp,
|
|
fmt_bit_depth);
|
|
|
|
dce110_opp_program_clamping_and_pixel_encoding(
|
|
opp,
|
|
clamping);
|
|
|
|
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
|
program_formatter_reset_dig_resync_fifo(opp);
|
|
|
|
return;
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static void dce60_opp_program_fmt(
|
|
struct output_pixel_processor *opp,
|
|
struct bit_depth_reduction_params *fmt_bit_depth,
|
|
struct clamping_and_pixel_encoding_params *clamping)
|
|
{
|
|
/* dithering is affected by <CrtcSourceSelect>, hence should be
|
|
* programmed afterwards */
|
|
|
|
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
|
program_formatter_420_memory(opp);
|
|
|
|
dce60_opp_program_bit_depth_reduction(
|
|
opp,
|
|
fmt_bit_depth);
|
|
|
|
dce60_opp_program_clamping_and_pixel_encoding(
|
|
opp,
|
|
clamping);
|
|
|
|
if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
|
|
program_formatter_reset_dig_resync_fifo(opp);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
/*****************************************/
|
|
/* Constructor, Destructor */
|
|
/*****************************************/
|
|
|
|
static const struct opp_funcs funcs = {
|
|
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
|
|
.opp_destroy = dce110_opp_destroy,
|
|
.opp_program_fmt = dce110_opp_program_fmt,
|
|
.opp_program_bit_depth_reduction = dce110_opp_program_bit_depth_reduction
|
|
};
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
static const struct opp_funcs dce60_opp_funcs = {
|
|
.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
|
|
.opp_destroy = dce110_opp_destroy,
|
|
.opp_program_fmt = dce60_opp_program_fmt,
|
|
.opp_program_bit_depth_reduction = dce60_opp_program_bit_depth_reduction
|
|
};
|
|
#endif
|
|
|
|
void dce110_opp_construct(struct dce110_opp *opp110,
|
|
struct dc_context *ctx,
|
|
uint32_t inst,
|
|
const struct dce_opp_registers *regs,
|
|
const struct dce_opp_shift *opp_shift,
|
|
const struct dce_opp_mask *opp_mask)
|
|
{
|
|
opp110->base.funcs = &funcs;
|
|
|
|
opp110->base.ctx = ctx;
|
|
|
|
opp110->base.inst = inst;
|
|
|
|
opp110->regs = regs;
|
|
opp110->opp_shift = opp_shift;
|
|
opp110->opp_mask = opp_mask;
|
|
}
|
|
|
|
#if defined(CONFIG_DRM_AMD_DC_SI)
|
|
void dce60_opp_construct(struct dce110_opp *opp110,
|
|
struct dc_context *ctx,
|
|
uint32_t inst,
|
|
const struct dce_opp_registers *regs,
|
|
const struct dce_opp_shift *opp_shift,
|
|
const struct dce_opp_mask *opp_mask)
|
|
{
|
|
opp110->base.funcs = &dce60_opp_funcs;
|
|
|
|
opp110->base.ctx = ctx;
|
|
|
|
opp110->base.inst = inst;
|
|
|
|
opp110->regs = regs;
|
|
opp110->opp_shift = opp_shift;
|
|
opp110->opp_mask = opp_mask;
|
|
}
|
|
#endif
|
|
|
|
void dce110_opp_destroy(struct output_pixel_processor **opp)
|
|
{
|
|
if (*opp)
|
|
kfree(FROM_DCE11_OPP(*opp));
|
|
*opp = NULL;
|
|
}
|
|
|