608 lines
14 KiB
C
608 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/gfp.h>
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#include <linux/workqueue.h>
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#include <crypto/internal/skcipher.h>
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#include "nitrox_common.h"
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#include "nitrox_dev.h"
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#include "nitrox_req.h"
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#include "nitrox_csr.h"
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/* SLC_STORE_INFO */
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#define MIN_UDD_LEN 16
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/* PKT_IN_HDR + SLC_STORE_INFO */
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#define FDATA_SIZE 32
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/* Base destination port for the solicited requests */
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#define SOLICIT_BASE_DPORT 256
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#define REQ_NOT_POSTED 1
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#define REQ_BACKLOG 2
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#define REQ_POSTED 3
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/*
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* Response codes from SE microcode
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* 0x00 - Success
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* Completion with no error
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* 0x43 - ERR_GC_DATA_LEN_INVALID
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* Invalid Data length if Encryption Data length is
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* less than 16 bytes for AES-XTS and AES-CTS.
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* 0x45 - ERR_GC_CTX_LEN_INVALID
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* Invalid context length: CTXL != 23 words.
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* 0x4F - ERR_GC_DOCSIS_CIPHER_INVALID
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* DOCSIS support is enabled with other than
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* AES/DES-CBC mode encryption.
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* 0x50 - ERR_GC_DOCSIS_OFFSET_INVALID
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* Authentication offset is other than 0 with
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* Encryption IV source = 0.
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* Authentication offset is other than 8 (DES)/16 (AES)
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* with Encryption IV source = 1
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* 0x51 - ERR_GC_CRC32_INVALID_SELECTION
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* CRC32 is enabled for other than DOCSIS encryption.
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* 0x52 - ERR_GC_AES_CCM_FLAG_INVALID
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* Invalid flag options in AES-CCM IV.
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*/
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static inline int incr_index(int index, int count, int max)
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{
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if ((index + count) >= max)
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index = index + count - max;
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else
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index += count;
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return index;
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}
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static void softreq_unmap_sgbufs(struct nitrox_softreq *sr)
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{
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struct nitrox_device *ndev = sr->ndev;
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struct device *dev = DEV(ndev);
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dma_unmap_sg(dev, sr->in.sg, sg_nents(sr->in.sg),
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DMA_BIDIRECTIONAL);
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dma_unmap_single(dev, sr->in.sgcomp_dma, sr->in.sgcomp_len,
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DMA_TO_DEVICE);
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kfree(sr->in.sgcomp);
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sr->in.sg = NULL;
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sr->in.sgmap_cnt = 0;
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dma_unmap_sg(dev, sr->out.sg, sg_nents(sr->out.sg),
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DMA_BIDIRECTIONAL);
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dma_unmap_single(dev, sr->out.sgcomp_dma, sr->out.sgcomp_len,
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DMA_TO_DEVICE);
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kfree(sr->out.sgcomp);
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sr->out.sg = NULL;
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sr->out.sgmap_cnt = 0;
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}
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static void softreq_destroy(struct nitrox_softreq *sr)
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{
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softreq_unmap_sgbufs(sr);
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kfree(sr);
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}
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/**
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* create_sg_component - create SG componets for N5 device.
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* @sr: Request structure
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* @sgtbl: SG table
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* @map_nents: number of dma mapped entries
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*
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* Component structure
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*
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* 63 48 47 32 31 16 15 0
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* --------------------------------------
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* | LEN0 | LEN1 | LEN2 | LEN3 |
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* |-------------------------------------
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* | PTR0 |
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* --------------------------------------
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* | PTR1 |
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* --------------------------------------
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* | PTR2 |
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* --------------------------------------
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* | PTR3 |
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* --------------------------------------
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*
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* Returns 0 if success or a negative errno code on error.
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*/
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static int create_sg_component(struct nitrox_softreq *sr,
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struct nitrox_sgtable *sgtbl, int map_nents)
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{
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struct nitrox_device *ndev = sr->ndev;
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struct nitrox_sgcomp *sgcomp;
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struct scatterlist *sg;
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dma_addr_t dma;
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size_t sz_comp;
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int i, j, nr_sgcomp;
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nr_sgcomp = roundup(map_nents, 4) / 4;
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/* each component holds 4 dma pointers */
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sz_comp = nr_sgcomp * sizeof(*sgcomp);
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sgcomp = kzalloc(sz_comp, sr->gfp);
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if (!sgcomp)
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return -ENOMEM;
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sgtbl->sgcomp = sgcomp;
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sg = sgtbl->sg;
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/* populate device sg component */
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for (i = 0; i < nr_sgcomp; i++) {
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for (j = 0; j < 4 && sg; j++) {
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sgcomp[i].len[j] = cpu_to_be16(sg_dma_len(sg));
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sgcomp[i].dma[j] = cpu_to_be64(sg_dma_address(sg));
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sg = sg_next(sg);
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}
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}
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/* map the device sg component */
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dma = dma_map_single(DEV(ndev), sgtbl->sgcomp, sz_comp, DMA_TO_DEVICE);
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if (dma_mapping_error(DEV(ndev), dma)) {
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kfree(sgtbl->sgcomp);
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sgtbl->sgcomp = NULL;
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return -ENOMEM;
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}
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sgtbl->sgcomp_dma = dma;
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sgtbl->sgcomp_len = sz_comp;
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return 0;
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}
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/**
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* dma_map_inbufs - DMA map input sglist and creates sglist component
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* for N5 device.
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* @sr: Request structure
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* @req: Crypto request structre
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*
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* Returns 0 if successful or a negative errno code on error.
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*/
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static int dma_map_inbufs(struct nitrox_softreq *sr,
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struct se_crypto_request *req)
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{
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struct device *dev = DEV(sr->ndev);
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struct scatterlist *sg;
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int i, nents, ret = 0;
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nents = dma_map_sg(dev, req->src, sg_nents(req->src),
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DMA_BIDIRECTIONAL);
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if (!nents)
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return -EINVAL;
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for_each_sg(req->src, sg, nents, i)
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sr->in.total_bytes += sg_dma_len(sg);
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sr->in.sg = req->src;
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sr->in.sgmap_cnt = nents;
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ret = create_sg_component(sr, &sr->in, sr->in.sgmap_cnt);
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if (ret)
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goto incomp_err;
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return 0;
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incomp_err:
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dma_unmap_sg(dev, req->src, sg_nents(req->src), DMA_BIDIRECTIONAL);
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sr->in.sgmap_cnt = 0;
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return ret;
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}
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static int dma_map_outbufs(struct nitrox_softreq *sr,
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struct se_crypto_request *req)
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{
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struct device *dev = DEV(sr->ndev);
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int nents, ret = 0;
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nents = dma_map_sg(dev, req->dst, sg_nents(req->dst),
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DMA_BIDIRECTIONAL);
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if (!nents)
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return -EINVAL;
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sr->out.sg = req->dst;
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sr->out.sgmap_cnt = nents;
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ret = create_sg_component(sr, &sr->out, sr->out.sgmap_cnt);
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if (ret)
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goto outcomp_map_err;
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return 0;
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outcomp_map_err:
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dma_unmap_sg(dev, req->dst, sg_nents(req->dst), DMA_BIDIRECTIONAL);
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sr->out.sgmap_cnt = 0;
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sr->out.sg = NULL;
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return ret;
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}
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static inline int softreq_map_iobuf(struct nitrox_softreq *sr,
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struct se_crypto_request *creq)
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{
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int ret;
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ret = dma_map_inbufs(sr, creq);
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if (ret)
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return ret;
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ret = dma_map_outbufs(sr, creq);
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if (ret)
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softreq_unmap_sgbufs(sr);
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return ret;
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}
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static inline void backlog_list_add(struct nitrox_softreq *sr,
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struct nitrox_cmdq *cmdq)
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{
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INIT_LIST_HEAD(&sr->backlog);
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spin_lock_bh(&cmdq->backlog_qlock);
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list_add_tail(&sr->backlog, &cmdq->backlog_head);
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atomic_inc(&cmdq->backlog_count);
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atomic_set(&sr->status, REQ_BACKLOG);
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spin_unlock_bh(&cmdq->backlog_qlock);
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}
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static inline void response_list_add(struct nitrox_softreq *sr,
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struct nitrox_cmdq *cmdq)
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{
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INIT_LIST_HEAD(&sr->response);
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spin_lock_bh(&cmdq->resp_qlock);
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list_add_tail(&sr->response, &cmdq->response_head);
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spin_unlock_bh(&cmdq->resp_qlock);
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}
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static inline void response_list_del(struct nitrox_softreq *sr,
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struct nitrox_cmdq *cmdq)
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{
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spin_lock_bh(&cmdq->resp_qlock);
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list_del(&sr->response);
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spin_unlock_bh(&cmdq->resp_qlock);
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}
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static struct nitrox_softreq *
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get_first_response_entry(struct nitrox_cmdq *cmdq)
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{
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return list_first_entry_or_null(&cmdq->response_head,
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struct nitrox_softreq, response);
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}
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static inline bool cmdq_full(struct nitrox_cmdq *cmdq, int qlen)
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{
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if (atomic_inc_return(&cmdq->pending_count) > qlen) {
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atomic_dec(&cmdq->pending_count);
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/* sync with other cpus */
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smp_mb__after_atomic();
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return true;
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}
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/* sync with other cpus */
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smp_mb__after_atomic();
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return false;
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}
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/**
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* post_se_instr - Post SE instruction to Packet Input ring
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* @sr: Request structure
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* @cmdq: Command queue structure
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*
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* Returns 0 if successful or a negative error code,
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* if no space in ring.
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*/
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static void post_se_instr(struct nitrox_softreq *sr,
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struct nitrox_cmdq *cmdq)
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{
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struct nitrox_device *ndev = sr->ndev;
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int idx;
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u8 *ent;
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spin_lock_bh(&cmdq->cmd_qlock);
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idx = cmdq->write_idx;
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/* copy the instruction */
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ent = cmdq->base + (idx * cmdq->instr_size);
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memcpy(ent, &sr->instr, cmdq->instr_size);
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atomic_set(&sr->status, REQ_POSTED);
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response_list_add(sr, cmdq);
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sr->tstamp = jiffies;
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/* flush the command queue updates */
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dma_wmb();
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/* Ring doorbell with count 1 */
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writeq(1, cmdq->dbell_csr_addr);
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cmdq->write_idx = incr_index(idx, 1, ndev->qlen);
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spin_unlock_bh(&cmdq->cmd_qlock);
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/* increment the posted command count */
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atomic64_inc(&ndev->stats.posted);
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}
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static int post_backlog_cmds(struct nitrox_cmdq *cmdq)
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{
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struct nitrox_device *ndev = cmdq->ndev;
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struct nitrox_softreq *sr, *tmp;
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int ret = 0;
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if (!atomic_read(&cmdq->backlog_count))
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return 0;
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spin_lock_bh(&cmdq->backlog_qlock);
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list_for_each_entry_safe(sr, tmp, &cmdq->backlog_head, backlog) {
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/* submit until space available */
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if (unlikely(cmdq_full(cmdq, ndev->qlen))) {
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ret = -ENOSPC;
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break;
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}
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/* delete from backlog list */
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list_del(&sr->backlog);
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atomic_dec(&cmdq->backlog_count);
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/* sync with other cpus */
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smp_mb__after_atomic();
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/* post the command */
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post_se_instr(sr, cmdq);
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}
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spin_unlock_bh(&cmdq->backlog_qlock);
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return ret;
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}
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static int nitrox_enqueue_request(struct nitrox_softreq *sr)
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{
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struct nitrox_cmdq *cmdq = sr->cmdq;
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struct nitrox_device *ndev = sr->ndev;
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/* try to post backlog requests */
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post_backlog_cmds(cmdq);
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if (unlikely(cmdq_full(cmdq, ndev->qlen))) {
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if (!(sr->flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
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/* increment drop count */
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atomic64_inc(&ndev->stats.dropped);
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return -ENOSPC;
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}
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/* add to backlog list */
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backlog_list_add(sr, cmdq);
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return -EINPROGRESS;
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}
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post_se_instr(sr, cmdq);
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return -EINPROGRESS;
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}
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/**
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* nitrox_process_se_request - Send request to SE core
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* @ndev: NITROX device
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* @req: Crypto request
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* @callback: Completion callback
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* @cb_arg: Completion callback arguments
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*
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* Returns 0 on success, or a negative error code.
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*/
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int nitrox_process_se_request(struct nitrox_device *ndev,
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struct se_crypto_request *req,
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completion_t callback,
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void *cb_arg)
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{
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struct nitrox_softreq *sr;
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dma_addr_t ctx_handle = 0;
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int qno, ret = 0;
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if (!nitrox_ready(ndev))
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return -ENODEV;
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sr = kzalloc(sizeof(*sr), req->gfp);
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if (!sr)
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return -ENOMEM;
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sr->ndev = ndev;
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sr->flags = req->flags;
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sr->gfp = req->gfp;
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sr->callback = callback;
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sr->cb_arg = cb_arg;
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atomic_set(&sr->status, REQ_NOT_POSTED);
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sr->resp.orh = req->orh;
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sr->resp.completion = req->comp;
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ret = softreq_map_iobuf(sr, req);
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if (ret) {
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kfree(sr);
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return ret;
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}
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/* get the context handle */
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if (req->ctx_handle) {
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struct ctx_hdr *hdr;
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u8 *ctx_ptr;
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ctx_ptr = (u8 *)(uintptr_t)req->ctx_handle;
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hdr = (struct ctx_hdr *)(ctx_ptr - sizeof(struct ctx_hdr));
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ctx_handle = hdr->ctx_dma;
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}
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/* select the queue */
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qno = smp_processor_id() % ndev->nr_queues;
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sr->cmdq = &ndev->pkt_inq[qno];
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/*
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* 64-Byte Instruction Format
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*
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* ----------------------
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* | DPTR0 | 8 bytes
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* ----------------------
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* | PKT_IN_INSTR_HDR | 8 bytes
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* ----------------------
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* | PKT_IN_HDR | 16 bytes
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* ----------------------
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* | SLC_INFO | 16 bytes
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* ----------------------
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* | Front data | 16 bytes
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* ----------------------
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*/
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/* fill the packet instruction */
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/* word 0 */
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sr->instr.dptr0 = cpu_to_be64(sr->in.sgcomp_dma);
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/* word 1 */
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sr->instr.ih.value = 0;
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sr->instr.ih.s.g = 1;
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sr->instr.ih.s.gsz = sr->in.sgmap_cnt;
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sr->instr.ih.s.ssz = sr->out.sgmap_cnt;
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sr->instr.ih.s.fsz = FDATA_SIZE + sizeof(struct gphdr);
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sr->instr.ih.s.tlen = sr->instr.ih.s.fsz + sr->in.total_bytes;
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sr->instr.ih.bev = cpu_to_be64(sr->instr.ih.value);
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/* word 2 */
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sr->instr.irh.value[0] = 0;
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sr->instr.irh.s.uddl = MIN_UDD_LEN;
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/* context length in 64-bit words */
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sr->instr.irh.s.ctxl = (req->ctrl.s.ctxl / 8);
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/* offset from solicit base port 256 */
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sr->instr.irh.s.destport = SOLICIT_BASE_DPORT + qno;
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sr->instr.irh.s.ctxc = req->ctrl.s.ctxc;
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sr->instr.irh.s.arg = req->ctrl.s.arg;
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sr->instr.irh.s.opcode = req->opcode;
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sr->instr.irh.bev[0] = cpu_to_be64(sr->instr.irh.value[0]);
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/* word 3 */
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sr->instr.irh.s.ctxp = cpu_to_be64(ctx_handle);
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/* word 4 */
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sr->instr.slc.value[0] = 0;
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sr->instr.slc.s.ssz = sr->out.sgmap_cnt;
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sr->instr.slc.bev[0] = cpu_to_be64(sr->instr.slc.value[0]);
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/* word 5 */
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sr->instr.slc.s.rptr = cpu_to_be64(sr->out.sgcomp_dma);
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/*
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* No conversion for front data,
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* It goes into payload
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* put GP Header in front data
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*/
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sr->instr.fdata[0] = *((u64 *)&req->gph);
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sr->instr.fdata[1] = 0;
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ret = nitrox_enqueue_request(sr);
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if (ret == -ENOSPC)
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goto send_fail;
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return ret;
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send_fail:
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softreq_destroy(sr);
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return ret;
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}
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static inline int cmd_timeout(unsigned long tstamp, unsigned long timeout)
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{
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return time_after_eq(jiffies, (tstamp + timeout));
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}
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void backlog_qflush_work(struct work_struct *work)
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{
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struct nitrox_cmdq *cmdq;
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cmdq = container_of(work, struct nitrox_cmdq, backlog_qflush);
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post_backlog_cmds(cmdq);
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}
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static bool sr_completed(struct nitrox_softreq *sr)
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{
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u64 orh = READ_ONCE(*sr->resp.orh);
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unsigned long timeout = jiffies + msecs_to_jiffies(1);
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if ((orh != PENDING_SIG) && (orh & 0xff))
|
|
return true;
|
|
|
|
while (READ_ONCE(*sr->resp.completion) == PENDING_SIG) {
|
|
if (time_after(jiffies, timeout)) {
|
|
pr_err("comp not done\n");
|
|
return false;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* process_response_list - process completed requests
|
|
* @cmdq: Command queue structure
|
|
*
|
|
* Returns the number of responses processed.
|
|
*/
|
|
static void process_response_list(struct nitrox_cmdq *cmdq)
|
|
{
|
|
struct nitrox_device *ndev = cmdq->ndev;
|
|
struct nitrox_softreq *sr;
|
|
int req_completed = 0, err = 0, budget;
|
|
completion_t callback;
|
|
void *cb_arg;
|
|
|
|
/* check all pending requests */
|
|
budget = atomic_read(&cmdq->pending_count);
|
|
|
|
while (req_completed < budget) {
|
|
sr = get_first_response_entry(cmdq);
|
|
if (!sr)
|
|
break;
|
|
|
|
if (atomic_read(&sr->status) != REQ_POSTED)
|
|
break;
|
|
|
|
/* check orh and completion bytes updates */
|
|
if (!sr_completed(sr)) {
|
|
/* request not completed, check for timeout */
|
|
if (!cmd_timeout(sr->tstamp, ndev->timeout))
|
|
break;
|
|
dev_err_ratelimited(DEV(ndev),
|
|
"Request timeout, orh 0x%016llx\n",
|
|
READ_ONCE(*sr->resp.orh));
|
|
}
|
|
atomic_dec(&cmdq->pending_count);
|
|
atomic64_inc(&ndev->stats.completed);
|
|
/* sync with other cpus */
|
|
smp_mb__after_atomic();
|
|
/* remove from response list */
|
|
response_list_del(sr, cmdq);
|
|
/* ORH error code */
|
|
err = READ_ONCE(*sr->resp.orh) & 0xff;
|
|
callback = sr->callback;
|
|
cb_arg = sr->cb_arg;
|
|
softreq_destroy(sr);
|
|
if (callback)
|
|
callback(cb_arg, err);
|
|
|
|
req_completed++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* pkt_slc_resp_tasklet - post processing of SE responses
|
|
*/
|
|
void pkt_slc_resp_tasklet(unsigned long data)
|
|
{
|
|
struct nitrox_q_vector *qvec = (void *)(uintptr_t)(data);
|
|
struct nitrox_cmdq *cmdq = qvec->cmdq;
|
|
union nps_pkt_slc_cnts slc_cnts;
|
|
|
|
/* read completion count */
|
|
slc_cnts.value = readq(cmdq->compl_cnt_csr_addr);
|
|
/* resend the interrupt if more work to do */
|
|
slc_cnts.s.resend = 1;
|
|
|
|
process_response_list(cmdq);
|
|
|
|
/*
|
|
* clear the interrupt with resend bit enabled,
|
|
* MSI-X interrupt generates if Completion count > Threshold
|
|
*/
|
|
writeq(slc_cnts.value, cmdq->compl_cnt_csr_addr);
|
|
|
|
if (atomic_read(&cmdq->backlog_count))
|
|
schedule_work(&cmdq->backlog_qflush);
|
|
}
|