120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt8192-clk.h>
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static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
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.set_ofs = 0xe08,
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.clr_ofs = 0xe04,
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.sta_ofs = 0xe00,
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};
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#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
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GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \
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&mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
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static const struct mtk_gate imp_iic_wrap_c_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C10, "imp_iic_wrap_c_i2c10", "infra_i2c0", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C11, "imp_iic_wrap_c_i2c11", "infra_i2c0", 1),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C12, "imp_iic_wrap_c_i2c12", "infra_i2c0", 2),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_C_I2C13, "imp_iic_wrap_c_i2c13", "infra_i2c0", 3),
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};
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static const struct mtk_gate imp_iic_wrap_e_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_E_I2C3, "imp_iic_wrap_e_i2c3", "infra_i2c0", 0),
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};
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static const struct mtk_gate imp_iic_wrap_n_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C0, "imp_iic_wrap_n_i2c0", "infra_i2c0", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_N_I2C6, "imp_iic_wrap_n_i2c6", "infra_i2c0", 1),
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};
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static const struct mtk_gate imp_iic_wrap_s_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "infra_i2c0", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C8, "imp_iic_wrap_s_i2c8", "infra_i2c0", 1),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C9, "imp_iic_wrap_s_i2c9", "infra_i2c0", 2),
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};
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static const struct mtk_gate imp_iic_wrap_w_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C5, "imp_iic_wrap_w_i2c5", "infra_i2c0", 0),
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};
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static const struct mtk_gate imp_iic_wrap_ws_clks[] = {
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C1, "imp_iic_wrap_ws_i2c1", "infra_i2c0", 0),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C2, "imp_iic_wrap_ws_i2c2", "infra_i2c0", 1),
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GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_WS_I2C4, "imp_iic_wrap_ws_i2c4", "infra_i2c0", 2),
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};
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static const struct mtk_clk_desc imp_iic_wrap_c_desc = {
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.clks = imp_iic_wrap_c_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_c_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_e_desc = {
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.clks = imp_iic_wrap_e_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_e_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_n_desc = {
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.clks = imp_iic_wrap_n_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_n_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_s_desc = {
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.clks = imp_iic_wrap_s_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_w_desc = {
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.clks = imp_iic_wrap_w_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks),
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};
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static const struct mtk_clk_desc imp_iic_wrap_ws_desc = {
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.clks = imp_iic_wrap_ws_clks,
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.num_clks = ARRAY_SIZE(imp_iic_wrap_ws_clks),
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};
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static const struct of_device_id of_match_clk_mt8192_imp_iic_wrap[] = {
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{
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.compatible = "mediatek,mt8192-imp_iic_wrap_c",
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.data = &imp_iic_wrap_c_desc,
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}, {
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.compatible = "mediatek,mt8192-imp_iic_wrap_e",
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.data = &imp_iic_wrap_e_desc,
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}, {
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.compatible = "mediatek,mt8192-imp_iic_wrap_n",
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.data = &imp_iic_wrap_n_desc,
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}, {
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.compatible = "mediatek,mt8192-imp_iic_wrap_s",
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.data = &imp_iic_wrap_s_desc,
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}, {
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.compatible = "mediatek,mt8192-imp_iic_wrap_w",
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.data = &imp_iic_wrap_w_desc,
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}, {
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.compatible = "mediatek,mt8192-imp_iic_wrap_ws",
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.data = &imp_iic_wrap_ws_desc,
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}, {
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/* sentinel */
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}
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};
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static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {
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.probe = mtk_clk_simple_probe,
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.driver = {
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.name = "clk-mt8192-imp_iic_wrap",
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.of_match_table = of_match_clk_mt8192_imp_iic_wrap,
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},
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};
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builtin_platform_driver(clk_mt8192_imp_iic_wrap_drv);
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