152 lines
5.2 KiB
C
152 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
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* which was based on arch/arm/include/io.h
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*
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* Copyright (C) 1996-2000 Russell King
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2014 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_MMIO_H
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#define _ASM_RISCV_MMIO_H
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#include <linux/types.h>
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#include <asm/mmiowb.h>
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/* Generic IO read/write. These perform native-endian accesses. */
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#define __raw_writeb __raw_writeb
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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{
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asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writew __raw_writew
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static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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{
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asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#define __raw_writel __raw_writel
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static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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{
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asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#ifdef CONFIG_64BIT
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#define __raw_writeq __raw_writeq
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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{
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asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
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}
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#endif
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#define __raw_readb __raw_readb
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static inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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u8 val;
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asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readw __raw_readw
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static inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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u16 val;
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asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#define __raw_readl __raw_readl
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static inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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u32 val;
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asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#ifdef CONFIG_64BIT
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#define __raw_readq __raw_readq
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static inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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u64 val;
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asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
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return val;
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}
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#endif
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/*
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* Unordered I/O memory access primitives. These are even more relaxed than
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* the relaxed versions, as they don't even order accesses between successive
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* operations to the I/O regions.
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*/
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#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
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#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
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#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
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#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
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#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
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#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
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#ifdef CONFIG_64BIT
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#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
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#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
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#endif
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/*
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* Relaxed I/O memory access primitives. These follow the Device memory
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* ordering rules but do not guarantee any ordering relative to Normal memory
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* accesses. These are defined to order the indicated access (either a read or
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* write) with all other I/O memory accesses to the same peripheral. Since the
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* platform specification defines that all I/O regions are strongly ordered on
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* channel 0, no explicit fences are required to enforce this ordering.
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*/
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/* FIXME: These are now the same as asm-generic */
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#define __io_rbr() do {} while (0)
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#define __io_rar() do {} while (0)
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#define __io_rbw() do {} while (0)
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#define __io_raw() do {} while (0)
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#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
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#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
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#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
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#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
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#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
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#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
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#ifdef CONFIG_64BIT
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#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
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#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
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#endif
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/*
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* I/O memory access primitives. Reads are ordered relative to any following
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* Normal memory read and delay() loop. Writes are ordered relative to any
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* prior Normal memory write. The memory barriers here are necessary as RISC-V
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* doesn't define any ordering between the memory space and the I/O space.
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*/
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#define __io_br() do {} while (0)
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#define __io_ar(v) ({ __asm__ __volatile__ ("fence i,ir" : : : "memory"); })
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#define __io_bw() ({ __asm__ __volatile__ ("fence w,o" : : : "memory"); })
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#define __io_aw() mmiowb_set_pending()
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#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
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#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
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#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
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#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
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#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
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#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
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#ifdef CONFIG_64BIT
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#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
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#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
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#endif
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#endif /* _ASM_RISCV_MMIO_H */
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