569 lines
16 KiB
C
569 lines
16 KiB
C
/*
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* TX4939 setup routines
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* Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
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* and RBTX49xx patch from CELF patch archive.
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*
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* 2003-2005 (c) MontaVista Software, Inc.
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* (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/notifier.h>
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#include <linux/device.h>
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#include <linux/ethtool.h>
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#include <linux/param.h>
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#include <linux/ptrace.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/txx9/ndfmc.h>
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#include <asm/reboot.h>
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#include <asm/traps.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9tmr.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/dmac.h>
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#include <asm/txx9/tx4939.h>
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static void __init tx4939_wdr_init(void)
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{
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/* report watchdog reset status */
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if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
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pr_warn("Watchdog reset detected at 0x%lx\n",
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read_c0_errorepc());
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/* clear WatchDogReset (W1C) */
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tx4939_ccfg_set(TX4939_CCFG_WDRST);
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/* do reset on watchdog */
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tx4939_ccfg_set(TX4939_CCFG_WR);
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}
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void __init tx4939_wdt_init(void)
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{
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txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
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}
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static void tx4939_machine_restart(char *command)
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{
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local_irq_disable();
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pr_emerg("Rebooting (with %s watchdog reset)...\n",
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(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
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"external" : "internal");
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/* clear watchdog status */
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tx4939_ccfg_set(TX4939_CCFG_WDRST); /* W1C */
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txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
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while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
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;
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mdelay(10);
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if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
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pr_emerg("Rebooting (with internal watchdog reset)...\n");
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/* External WDRST failed. Do internal watchdog reset */
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tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
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}
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/* fallback */
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(*_machine_halt)();
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}
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void show_registers(struct pt_regs *regs);
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static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
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{
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int data = regs->cp0_cause & 4;
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console_verbose();
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pr_err("%cBE exception at %#lx\n",
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data ? 'D' : 'I', regs->cp0_epc);
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pr_err("ccfg:%llx, toea:%llx\n",
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(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
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#ifdef CONFIG_PCI
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tx4927_report_pcic_status();
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#endif
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show_registers(regs);
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panic("BusError!");
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}
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static void __init tx4939_be_init(void)
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{
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board_be_handler = tx4939_be_handler;
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}
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static struct resource tx4939_sdram_resource[4];
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static struct resource tx4939_sram_resource;
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#define TX4939_SRAM_SIZE 0x800
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void __init tx4939_setup(void)
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{
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int i;
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__u32 divmode;
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__u64 pcfg;
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unsigned int cpuclk = 0;
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txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
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TX4939_REG_SIZE);
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set_c0_config(TX49_CONF_CWFON);
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/* SDRAMC,EBUSC are configured by PROM */
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for (i = 0; i < 4; i++) {
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if (!(TX4939_EBUSC_CR(i) & 0x8))
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continue; /* disabled */
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txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
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txx9_ce_res[i].end =
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txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
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request_resource(&iomem_resource, &txx9_ce_res[i]);
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}
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/* clocks */
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if (txx9_master_clock) {
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/* calculate cpu_clock from master_clock */
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divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
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TX4939_CCFG_MULCLK_MASK;
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cpuclk = txx9_master_clock * 20 / 2;
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switch (divmode) {
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case TX4939_CCFG_MULCLK_8:
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cpuclk = cpuclk / 3 * 4 /* / 6 * 8 */; break;
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case TX4939_CCFG_MULCLK_9:
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cpuclk = cpuclk / 2 * 3 /* / 6 * 9 */; break;
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case TX4939_CCFG_MULCLK_10:
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cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
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case TX4939_CCFG_MULCLK_11:
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cpuclk = cpuclk / 6 * 11; break;
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case TX4939_CCFG_MULCLK_12:
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cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
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case TX4939_CCFG_MULCLK_13:
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cpuclk = cpuclk / 6 * 13; break;
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case TX4939_CCFG_MULCLK_14:
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cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
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case TX4939_CCFG_MULCLK_15:
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cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
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}
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txx9_cpu_clock = cpuclk;
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} else {
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if (txx9_cpu_clock == 0)
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txx9_cpu_clock = 400000000; /* 400MHz */
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/* calculate master_clock from cpu_clock */
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cpuclk = txx9_cpu_clock;
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divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
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TX4939_CCFG_MULCLK_MASK;
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switch (divmode) {
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case TX4939_CCFG_MULCLK_8:
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txx9_master_clock = cpuclk * 6 / 8; break;
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case TX4939_CCFG_MULCLK_9:
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txx9_master_clock = cpuclk * 6 / 9; break;
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case TX4939_CCFG_MULCLK_10:
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txx9_master_clock = cpuclk * 6 / 10; break;
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case TX4939_CCFG_MULCLK_11:
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txx9_master_clock = cpuclk * 6 / 11; break;
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case TX4939_CCFG_MULCLK_12:
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txx9_master_clock = cpuclk * 6 / 12; break;
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case TX4939_CCFG_MULCLK_13:
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txx9_master_clock = cpuclk * 6 / 13; break;
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case TX4939_CCFG_MULCLK_14:
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txx9_master_clock = cpuclk * 6 / 14; break;
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case TX4939_CCFG_MULCLK_15:
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txx9_master_clock = cpuclk * 6 / 15; break;
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}
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txx9_master_clock /= 10; /* * 2 / 20 */
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}
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/* calculate gbus_clock from cpu_clock */
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divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
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TX4939_CCFG_YDIVMODE_MASK;
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txx9_gbus_clock = txx9_cpu_clock;
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switch (divmode) {
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case TX4939_CCFG_YDIVMODE_2:
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txx9_gbus_clock /= 2; break;
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case TX4939_CCFG_YDIVMODE_3:
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txx9_gbus_clock /= 3; break;
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case TX4939_CCFG_YDIVMODE_5:
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txx9_gbus_clock /= 5; break;
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case TX4939_CCFG_YDIVMODE_6:
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txx9_gbus_clock /= 6; break;
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}
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/* change default value to udelay/mdelay take reasonable time */
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loops_per_jiffy = txx9_cpu_clock / HZ / 2;
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/* CCFG */
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tx4939_wdr_init();
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/* clear BusErrorOnWrite flag (W1C) */
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tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
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/* enable Timeout BusError */
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if (txx9_ccfg_toeon)
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tx4939_ccfg_set(TX4939_CCFG_TOE);
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/* DMA selection */
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txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
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/* Use external clock for external arbiter */
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if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
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txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
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pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str,
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(cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(txx9_gbus_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4939_ccfgptr->crir),
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____raw_readq(&tx4939_ccfgptr->ccfg),
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____raw_readq(&tx4939_ccfgptr->pcfg));
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pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
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(__u32)____raw_readq(&tx4939_ddrcptr->winen));
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for (i = 0; i < 4; i++) {
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__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
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if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
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continue; /* disabled */
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pr_cont(" #%d:%016llx", i, win);
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tx4939_sdram_resource[i].name = "DDR SDRAM";
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tx4939_sdram_resource[i].start =
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(unsigned long)(win >> 48) << 20;
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tx4939_sdram_resource[i].end =
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((((unsigned long)(win >> 32) & 0xffff) + 1) <<
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20) - 1;
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tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
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}
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pr_cont("\n");
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/* SRAM */
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if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
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unsigned int size = TX4939_SRAM_SIZE;
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tx4939_sram_resource.name = "SRAM";
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tx4939_sram_resource.start =
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(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
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& ~(size - 1);
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tx4939_sram_resource.end =
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tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
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tx4939_sram_resource.flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4939_sram_resource);
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}
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/* TMR */
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/* disable all timers */
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for (i = 0; i < TX4939_NR_TMR; i++)
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txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
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/* set PCIC1 reset (required to prevent hangup on BIST) */
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
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pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
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if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
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mdelay(1); /* at least 128 cpu clock */
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/* clear PCIC1 reset */
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txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
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} else {
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pr_info("%s: stop PCIC1\n", txx9_pcode_str);
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/* stop PCIC1 */
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
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}
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if (!(pcfg & TX4939_PCFG_ET0MODE)) {
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pr_info("%s: stop ETH0\n", txx9_pcode_str);
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
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}
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if (!(pcfg & TX4939_PCFG_ET1MODE)) {
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pr_info("%s: stop ETH1\n", txx9_pcode_str);
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
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txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
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}
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_machine_restart = tx4939_machine_restart;
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board_be_init = tx4939_be_init;
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}
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void __init tx4939_time_init(unsigned int tmrnr)
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{
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if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
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txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
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TXX9_IMCLK);
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}
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void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
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{
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int i;
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unsigned int ch_mask = 0;
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__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
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cts_mask |= ~1; /* only SIO0 have RTS/CTS */
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if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
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cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
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if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
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ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
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if (pcfg & TX4939_PCFG_SIO3MODE)
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ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
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for (i = 0; i < 4; i++) {
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if ((1 << i) & ch_mask)
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continue;
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txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
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TXX9_IRQ_BASE + TX4939_IR_SIO(i),
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i, sclk, (1 << i) & cts_mask);
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}
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}
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#if IS_ENABLED(CONFIG_TC35815)
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static u32 tx4939_get_eth_speed(struct net_device *dev)
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{
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struct ethtool_link_ksettings cmd;
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if (__ethtool_get_link_ksettings(dev, &cmd))
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return 100; /* default 100Mbps */
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return cmd.base.speed;
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}
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static int tx4939_netdev_event(struct notifier_block *this,
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unsigned long event,
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void *ptr)
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{
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struct net_device *dev = netdev_notifier_info_to_dev(ptr);
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if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
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__u64 bit = 0;
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if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
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bit = TX4939_PCFG_SPEED0;
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else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
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bit = TX4939_PCFG_SPEED1;
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if (bit) {
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if (tx4939_get_eth_speed(dev) == 100)
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txx9_set64(&tx4939_ccfgptr->pcfg, bit);
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else
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txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
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}
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block tx4939_netdev_notifier = {
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.notifier_call = tx4939_netdev_event,
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.priority = 1,
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};
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void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
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{
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u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
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if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
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txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
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if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
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txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
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register_netdevice_notifier(&tx4939_netdev_notifier);
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}
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#else
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void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
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{
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}
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#endif
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void __init tx4939_mtd_init(int ch)
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{
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struct physmap_flash_data pdata = {
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.width = TX4939_EBUSC_WIDTH(ch) / 8,
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};
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unsigned long start = txx9_ce_res[ch].start;
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unsigned long size = txx9_ce_res[ch].end - start + 1;
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if (!(TX4939_EBUSC_CR(ch) & 0x8))
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return; /* disabled */
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txx9_physmap_flash_init(ch, start, size, &pdata);
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}
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#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
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void __init tx4939_ata_init(void)
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{
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static struct resource ata0_res[] = {
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{
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.start = TX4939_ATA_REG_PHYS(0),
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.end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource ata1_res[] = {
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{
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.start = TX4939_ATA_REG_PHYS(1),
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.end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device ata0_dev = {
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.name = "tx4939ide",
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.id = 0,
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.num_resources = ARRAY_SIZE(ata0_res),
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.resource = ata0_res,
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};
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static struct platform_device ata1_dev = {
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.name = "tx4939ide",
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.id = 1,
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.num_resources = ARRAY_SIZE(ata1_res),
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.resource = ata1_res,
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};
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__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
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if (pcfg & TX4939_PCFG_ATA0MODE)
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platform_device_register(&ata0_dev);
|
|
if ((pcfg & (TX4939_PCFG_ATA1MODE |
|
|
TX4939_PCFG_ET1MODE |
|
|
TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
|
|
platform_device_register(&ata1_dev);
|
|
}
|
|
|
|
void __init tx4939_rtc_init(void)
|
|
{
|
|
static struct resource res[] = {
|
|
{
|
|
.start = TX4939_RTC_REG & 0xfffffffffULL,
|
|
.end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = TXX9_IRQ_BASE + TX4939_IR_RTC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
static struct platform_device rtc_dev = {
|
|
.name = "tx4939rtc",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(res),
|
|
.resource = res,
|
|
};
|
|
|
|
platform_device_register(&rtc_dev);
|
|
}
|
|
|
|
void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
|
|
unsigned char ch_mask, unsigned char wide_mask)
|
|
{
|
|
struct txx9ndfmc_platform_data plat_data = {
|
|
.shift = 1,
|
|
.gbus_clock = txx9_gbus_clock,
|
|
.hold = hold,
|
|
.spw = spw,
|
|
.flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD |
|
|
NDFMC_PLAT_FLAG_DUMMYWRITE,
|
|
.ch_mask = ch_mask,
|
|
.wide_mask = wide_mask,
|
|
};
|
|
txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
|
|
}
|
|
|
|
void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
|
|
{
|
|
struct txx9dmac_platform_data plat_data = {
|
|
.have_64bit_regs = true,
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
|
|
txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
|
|
TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
|
|
&plat_data);
|
|
}
|
|
}
|
|
|
|
void __init tx4939_aclc_init(void)
|
|
{
|
|
u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
|
|
|
|
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
|
|
txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
|
|
TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
|
|
}
|
|
|
|
void __init tx4939_sramc_init(void)
|
|
{
|
|
if (tx4939_sram_resource.start)
|
|
txx9_sramc_init(&tx4939_sram_resource);
|
|
}
|
|
|
|
void __init tx4939_rng_init(void)
|
|
{
|
|
static struct resource res = {
|
|
.start = TX4939_RNG_REG & 0xfffffffffULL,
|
|
.end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
static struct platform_device pdev = {
|
|
.name = "tx4939-rng",
|
|
.id = -1,
|
|
.num_resources = 1,
|
|
.resource = &res,
|
|
};
|
|
|
|
platform_device_register(&pdev);
|
|
}
|
|
|
|
static void __init tx4939_stop_unused_modules(void)
|
|
{
|
|
__u64 pcfg, rst = 0, ckd = 0;
|
|
char buf[128];
|
|
|
|
buf[0] = '\0';
|
|
local_irq_disable();
|
|
pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
|
|
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
|
TX4939_PCFG_I2SMODE_ACLC) {
|
|
rst |= TX4939_CLKCTR_ACLRST;
|
|
ckd |= TX4939_CLKCTR_ACLCKD;
|
|
strcat(buf, " ACLC");
|
|
}
|
|
if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
|
TX4939_PCFG_I2SMODE_I2S &&
|
|
(pcfg & TX4939_PCFG_I2SMODE_MASK) !=
|
|
TX4939_PCFG_I2SMODE_I2S_ALT) {
|
|
rst |= TX4939_CLKCTR_I2SRST;
|
|
ckd |= TX4939_CLKCTR_I2SCKD;
|
|
strcat(buf, " I2S");
|
|
}
|
|
if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
|
|
rst |= TX4939_CLKCTR_ATA0RST;
|
|
ckd |= TX4939_CLKCTR_ATA0CKD;
|
|
strcat(buf, " ATA0");
|
|
}
|
|
if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
|
|
rst |= TX4939_CLKCTR_ATA1RST;
|
|
ckd |= TX4939_CLKCTR_ATA1CKD;
|
|
strcat(buf, " ATA1");
|
|
}
|
|
if (pcfg & TX4939_PCFG_SPIMODE) {
|
|
rst |= TX4939_CLKCTR_SPIRST;
|
|
ckd |= TX4939_CLKCTR_SPICKD;
|
|
strcat(buf, " SPI");
|
|
}
|
|
if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
|
|
rst |= TX4939_CLKCTR_VPCRST;
|
|
ckd |= TX4939_CLKCTR_VPCCKD;
|
|
strcat(buf, " VPC");
|
|
}
|
|
if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
|
|
rst |= TX4939_CLKCTR_SIO2RST;
|
|
ckd |= TX4939_CLKCTR_SIO2CKD;
|
|
strcat(buf, " SIO2");
|
|
}
|
|
if (pcfg & TX4939_PCFG_SIO3MODE) {
|
|
rst |= TX4939_CLKCTR_SIO3RST;
|
|
ckd |= TX4939_CLKCTR_SIO3CKD;
|
|
strcat(buf, " SIO3");
|
|
}
|
|
if (rst | ckd) {
|
|
txx9_set64(&tx4939_ccfgptr->clkctr, rst);
|
|
txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
|
|
}
|
|
local_irq_enable();
|
|
if (buf[0])
|
|
pr_info("%s: stop%s\n", txx9_pcode_str, buf);
|
|
}
|
|
|
|
static int __init tx4939_late_init(void)
|
|
{
|
|
if (txx9_pcode != 0x4939)
|
|
return -ENODEV;
|
|
tx4939_stop_unused_modules();
|
|
return 0;
|
|
}
|
|
late_initcall(tx4939_late_init);
|