172 lines
3.6 KiB
C
172 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 ARM Ltd.
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*/
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#ifndef __ASM_MTE_KASAN_H
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#define __ASM_MTE_KASAN_H
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#include <asm/compiler.h>
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#include <asm/mte-def.h>
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#ifdef CONFIG_ARM64_MTE
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/*
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* These functions are meant to be only used from KASAN runtime through
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* the arch_*() interface defined in asm/memory.h.
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* These functions don't include system_supports_mte() checks,
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* as KASAN only calls them when MTE is supported and enabled.
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*/
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static inline u8 mte_get_ptr_tag(void *ptr)
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{
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/* Note: The format of KASAN tags is 0xF<x> */
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u8 tag = 0xF0 | (u8)(((u64)(ptr)) >> MTE_TAG_SHIFT);
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return tag;
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}
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/* Get allocation tag for the address. */
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static inline u8 mte_get_mem_tag(void *addr)
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{
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asm(__MTE_PREAMBLE "ldg %0, [%0]"
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: "+r" (addr));
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return mte_get_ptr_tag(addr);
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}
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/* Generate a random tag. */
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static inline u8 mte_get_random_tag(void)
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{
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void *addr;
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asm(__MTE_PREAMBLE "irg %0, %0"
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: "=r" (addr));
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return mte_get_ptr_tag(addr);
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}
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static inline u64 __stg_post(u64 p)
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{
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asm volatile(__MTE_PREAMBLE "stg %0, [%0], #16"
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: "+r"(p)
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:
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: "memory");
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return p;
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}
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static inline u64 __stzg_post(u64 p)
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{
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asm volatile(__MTE_PREAMBLE "stzg %0, [%0], #16"
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: "+r"(p)
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:
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: "memory");
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return p;
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}
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static inline void __dc_gva(u64 p)
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{
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asm volatile(__MTE_PREAMBLE "dc gva, %0" : : "r"(p) : "memory");
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}
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static inline void __dc_gzva(u64 p)
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{
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asm volatile(__MTE_PREAMBLE "dc gzva, %0" : : "r"(p) : "memory");
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}
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/*
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* Assign allocation tags for a region of memory based on the pointer tag.
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* Note: The address must be non-NULL and MTE_GRANULE_SIZE aligned and
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* size must be MTE_GRANULE_SIZE aligned.
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*/
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static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag,
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bool init)
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{
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u64 curr, mask, dczid, dczid_bs, dczid_dzp, end1, end2, end3;
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/* Read DC G(Z)VA block size from the system register. */
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dczid = read_cpuid(DCZID_EL0);
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dczid_bs = 4ul << (dczid & 0xf);
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dczid_dzp = (dczid >> 4) & 1;
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curr = (u64)__tag_set(addr, tag);
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mask = dczid_bs - 1;
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/* STG/STZG up to the end of the first block. */
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end1 = curr | mask;
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end3 = curr + size;
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/* DC GVA / GZVA in [end1, end2) */
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end2 = end3 & ~mask;
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/*
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* The following code uses STG on the first DC GVA block even if the
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* start address is aligned - it appears to be faster than an alignment
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* check + conditional branch. Also, if the range size is at least 2 DC
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* GVA blocks, the first two loops can use post-condition to save one
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* branch each.
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*/
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#define SET_MEMTAG_RANGE(stg_post, dc_gva) \
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do { \
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if (!dczid_dzp && size >= 2 * dczid_bs) {\
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do { \
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curr = stg_post(curr); \
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} while (curr < end1); \
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\
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do { \
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dc_gva(curr); \
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curr += dczid_bs; \
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} while (curr < end2); \
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} \
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\
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while (curr < end3) \
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curr = stg_post(curr); \
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} while (0)
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if (init)
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SET_MEMTAG_RANGE(__stzg_post, __dc_gzva);
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else
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SET_MEMTAG_RANGE(__stg_post, __dc_gva);
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#undef SET_MEMTAG_RANGE
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}
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void mte_enable_kernel_sync(void);
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void mte_enable_kernel_async(void);
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#else /* CONFIG_ARM64_MTE */
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static inline u8 mte_get_ptr_tag(void *ptr)
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{
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return 0xFF;
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}
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static inline u8 mte_get_mem_tag(void *addr)
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{
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return 0xFF;
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}
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static inline u8 mte_get_random_tag(void)
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{
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return 0xFF;
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}
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static inline void mte_set_mem_tag_range(void *addr, size_t size,
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u8 tag, bool init)
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{
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}
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static inline void mte_enable_kernel_sync(void)
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{
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}
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static inline void mte_enable_kernel_async(void)
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{
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}
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#endif /* CONFIG_ARM64_MTE */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_MTE_KASAN_H */
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