206 lines
7.2 KiB
C
206 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP2+ DMA driver
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*
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* Copyright (C) 2003 - 2008 Nokia Corporation
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
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* Graphics DMA and LCD DMA graphics tranformations
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* by Imre Deak <imre.deak@nokia.com>
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* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
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* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
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* Converted DMA library into platform driver
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* - G, Manjunath Kondaiah <manjugk@ti.com>
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/of.h>
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#include <linux/omap-dma.h>
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#include "soc.h"
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static const struct omap_dma_reg reg_map[] = {
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[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
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[GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
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[IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
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[IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
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[IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
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[IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
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[IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
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[IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
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[IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
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[IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
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[SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
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[OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
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[CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
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[CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
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[CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
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[CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
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/* Common register offsets */
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[CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
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[CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
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[CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
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[CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
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[CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
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[CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
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[CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
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[CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
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[CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
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[CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
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[CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
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[CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
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[CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
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/* Channel specific register offsets */
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[CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
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[CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
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[CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
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[CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
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[COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
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/* OMAP4 specific registers */
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[CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
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[CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
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[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
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};
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static unsigned configure_dma_errata(void)
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{
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unsigned errata = 0;
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/*
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* Errata applicable for OMAP2430ES1.0 and all omap2420
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*
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* I.
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* Erratum ID: Not Available
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* Inter Frame DMA buffering issue DMA will wrongly
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* buffer elements if packing and bursting is enabled. This might
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* result in data gets stalled in FIFO at the end of the block.
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* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
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* guarantee no data will stay in the DMA FIFO in case inter frame
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* buffering occurs
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*
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* II.
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* Erratum ID: Not Available
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* DMA may hang when several channels are used in parallel
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* In the following configuration, DMA channel hanging can occur:
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* a. Channel i, hardware synchronized, is enabled
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* b. Another channel (Channel x), software synchronized, is enabled.
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* c. Channel i is disabled before end of transfer
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* d. Channel i is reenabled.
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* e. Steps 1 to 4 are repeated a certain number of times.
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* f. A third channel (Channel y), software synchronized, is enabled.
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* Channel x and Channel y may hang immediately after step 'f'.
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* Workaround:
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* For any channel used - make sure NextLCH_ID is set to the value j.
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*/
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if (cpu_is_omap2420() || (cpu_is_omap2430() &&
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(omap_type() == OMAP2430_REV_ES1_0))) {
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SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
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SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
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}
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/*
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* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
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* after a transaction error.
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* Workaround: SW should explicitely disable the channel.
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*/
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if (cpu_class_is_omap2())
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SET_DMA_ERRATA(DMA_ERRATA_i378);
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/*
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* Erratum ID: i541: sDMA FIFO draining does not finish
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* If sDMA channel is disabled on the fly, sDMA enters standby even
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* through FIFO Drain is still in progress
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* Workaround: Put sDMA in NoStandby more before a logical channel is
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* disabled, then put it back to SmartStandby right after the channel
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* finishes FIFO draining.
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*/
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if (cpu_is_omap34xx())
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SET_DMA_ERRATA(DMA_ERRATA_i541);
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/*
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* Erratum ID: i88 : Special programming model needed to disable DMA
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* before end of block.
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* Workaround: software must ensure that the DMA is configured in No
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* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
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*/
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if (omap_type() == OMAP3430_REV_ES1_0)
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SET_DMA_ERRATA(DMA_ERRATA_i88);
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/*
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* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
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* read before the DMA controller finished disabling the channel.
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*/
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SET_DMA_ERRATA(DMA_ERRATA_3_3);
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/*
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* Erratum ID: Not Available
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* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
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* after secure sram context save and restore.
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* Work around: Hence we need to manually clear those IRQs to avoid
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* spurious interrupts. This affects only secure devices.
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*/
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if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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SET_DMA_ERRATA(DMA_ROMCODE_BUG);
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return errata;
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}
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static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
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/* external DMA requests when tusb6010 is used */
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{ "musb-hdrc.1.auto", "dmareq0", SDMA_FILTER_PARAM(2) },
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{ "musb-hdrc.1.auto", "dmareq1", SDMA_FILTER_PARAM(3) },
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{ "musb-hdrc.1.auto", "dmareq2", SDMA_FILTER_PARAM(14) }, /* OMAP2420 only */
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{ "musb-hdrc.1.auto", "dmareq3", SDMA_FILTER_PARAM(15) }, /* OMAP2420 only */
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{ "musb-hdrc.1.auto", "dmareq4", SDMA_FILTER_PARAM(16) }, /* OMAP2420 only */
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{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
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};
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static struct omap_dma_dev_attr dma_attr = {
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.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
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IS_CSSA_32 | IS_CDSA_32,
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.lch_count = 32,
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};
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struct omap_system_dma_plat_info dma_plat_info = {
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.reg_map = reg_map,
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.channel_stride = 0x60,
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.dma_attr = &dma_attr,
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};
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/* One time initializations */
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static int __init omap2_system_dma_init(void)
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{
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dma_plat_info.errata = configure_dma_errata();
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if (soc_is_omap24xx()) {
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/* DMA slave map for drivers not yet converted to DT */
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dma_plat_info.slave_map = omap24xx_sdma_dt_map;
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dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
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}
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if (!soc_is_omap242x())
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dma_attr.dev_caps |= IS_RW_PRIORITY;
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if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
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return 0;
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}
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omap_arch_initcall(omap2_system_dma_init);
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