444 lines
8.5 KiB
C
444 lines
8.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-omap1/mcbsp.c
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*
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* Copyright (C) 2008 Instituto Nokia de Tecnologia
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* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
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*
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* Multichannel mode not supported.
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*/
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/omap-dma.h>
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#include <mach/mux.h>
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#include "soc.h"
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#include <linux/platform_data/asoc-ti-mcbsp.h>
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#include <mach/irqs.h>
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#include "iomap.h"
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#define DPS_RSTCT2_PER_EN (1 << 0)
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#define DSP_RSTCT2_WD_PER_EN (1 << 1)
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static int dsp_use;
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static struct clk *api_clk;
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static struct clk *dsp_clk;
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static struct platform_device **omap_mcbsp_devices;
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static void omap1_mcbsp_request(unsigned int id)
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{
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/*
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* On 1510, 1610 and 1710, McBSP1 and McBSP3
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* are DSP public peripherals.
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*/
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if (id == 0 || id == 2) {
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if (dsp_use++ == 0) {
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api_clk = clk_get(NULL, "api_ck");
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dsp_clk = clk_get(NULL, "dsp_ck");
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if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
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clk_enable(api_clk);
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clk_enable(dsp_clk);
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/*
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* DSP external peripheral reset
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* FIXME: This should be moved to dsp code
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*/
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__raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
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DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
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}
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}
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}
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}
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static void omap1_mcbsp_free(unsigned int id)
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{
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if (id == 0 || id == 2) {
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if (--dsp_use == 0) {
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if (!IS_ERR(api_clk)) {
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clk_disable(api_clk);
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clk_put(api_clk);
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}
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if (!IS_ERR(dsp_clk)) {
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clk_disable(dsp_clk);
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clk_put(dsp_clk);
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}
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}
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}
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}
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static struct omap_mcbsp_ops omap1_mcbsp_ops = {
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.request = omap1_mcbsp_request,
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.free = omap1_mcbsp_free,
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};
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#define OMAP7XX_MCBSP1_BASE 0xfffb1000
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#define OMAP7XX_MCBSP2_BASE 0xfffb1800
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#define OMAP1510_MCBSP1_BASE 0xe1011800
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#define OMAP1510_MCBSP2_BASE 0xfffb1000
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#define OMAP1510_MCBSP3_BASE 0xe1017000
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#define OMAP1610_MCBSP1_BASE 0xe1011800
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#define OMAP1610_MCBSP2_BASE 0xfffb1000
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#define OMAP1610_MCBSP3_BASE 0xe1017000
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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struct resource omap7xx_mcbsp_res[][6] = {
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{
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{
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.start = OMAP7XX_MCBSP1_BASE,
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.end = OMAP7XX_MCBSP1_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_7XX_McBSP1RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_7XX_McBSP1TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 9,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 8,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.start = OMAP7XX_MCBSP2_BASE,
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.end = OMAP7XX_MCBSP2_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_7XX_McBSP2RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_7XX_McBSP2TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 11,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 10,
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.flags = IORESOURCE_DMA,
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},
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},
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};
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#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
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static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
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{
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.ops = &omap1_mcbsp_ops,
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},
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{
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.ops = &omap1_mcbsp_ops,
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},
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};
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#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
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#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
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#else
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#define omap7xx_mcbsp_res_0 NULL
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#define omap7xx_mcbsp_pdata NULL
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#define OMAP7XX_MCBSP_RES_SZ 0
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#define OMAP7XX_MCBSP_COUNT 0
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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struct resource omap15xx_mcbsp_res[][6] = {
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{
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{
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.start = OMAP1510_MCBSP1_BASE,
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.end = OMAP1510_MCBSP1_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_McBSP1RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_McBSP1TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 9,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 8,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.start = OMAP1510_MCBSP2_BASE,
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.end = OMAP1510_MCBSP2_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_1510_SPI_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_1510_SPI_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 17,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 16,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.start = OMAP1510_MCBSP3_BASE,
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.end = OMAP1510_MCBSP3_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_McBSP3RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_McBSP3TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 11,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 10,
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.flags = IORESOURCE_DMA,
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},
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},
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};
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#define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
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static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
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{
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.ops = &omap1_mcbsp_ops,
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},
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{
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.ops = &omap1_mcbsp_ops,
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},
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{
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.ops = &omap1_mcbsp_ops,
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},
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};
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#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
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#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
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#else
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#define omap15xx_mcbsp_res_0 NULL
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#define omap15xx_mcbsp_pdata NULL
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#define OMAP15XX_MCBSP_RES_SZ 0
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#define OMAP15XX_MCBSP_COUNT 0
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#endif
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#ifdef CONFIG_ARCH_OMAP16XX
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struct resource omap16xx_mcbsp_res[][6] = {
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{
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{
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.start = OMAP1610_MCBSP1_BASE,
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.end = OMAP1610_MCBSP1_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_McBSP1RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_McBSP1TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 9,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 8,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.start = OMAP1610_MCBSP2_BASE,
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.end = OMAP1610_MCBSP2_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_1610_McBSP2_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_1610_McBSP2_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 17,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 16,
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.flags = IORESOURCE_DMA,
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},
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},
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{
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{
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.start = OMAP1610_MCBSP3_BASE,
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.end = OMAP1610_MCBSP3_BASE + SZ_256,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "rx",
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.start = INT_McBSP3RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "tx",
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.start = INT_McBSP3TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.name = "rx",
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.start = 11,
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.flags = IORESOURCE_DMA,
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},
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{
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.name = "tx",
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.start = 10,
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.flags = IORESOURCE_DMA,
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},
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},
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};
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#define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
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static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
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{
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.ops = &omap1_mcbsp_ops,
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},
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{
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.ops = &omap1_mcbsp_ops,
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},
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{
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.ops = &omap1_mcbsp_ops,
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},
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};
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#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
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#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
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#else
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#define omap16xx_mcbsp_res_0 NULL
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#define omap16xx_mcbsp_pdata NULL
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#define OMAP16XX_MCBSP_RES_SZ 0
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#define OMAP16XX_MCBSP_COUNT 0
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#endif
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static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
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struct omap_mcbsp_platform_data *config, int size)
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{
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int i;
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omap_mcbsp_devices = kcalloc(size, sizeof(struct platform_device *),
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GFP_KERNEL);
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if (!omap_mcbsp_devices) {
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printk(KERN_ERR "Could not register McBSP devices\n");
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return;
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}
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for (i = 0; i < size; i++) {
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struct platform_device *new_mcbsp;
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int ret;
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new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
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if (!new_mcbsp)
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continue;
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platform_device_add_resources(new_mcbsp, &res[i * res_count],
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res_count);
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config[i].reg_size = 2;
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config[i].reg_step = 2;
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new_mcbsp->dev.platform_data = &config[i];
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ret = platform_device_add(new_mcbsp);
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if (ret) {
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platform_device_put(new_mcbsp);
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continue;
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}
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omap_mcbsp_devices[i] = new_mcbsp;
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}
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}
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static int __init omap1_mcbsp_init(void)
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{
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if (!cpu_class_is_omap1())
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return -ENODEV;
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if (cpu_is_omap7xx())
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omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
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OMAP7XX_MCBSP_RES_SZ,
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omap7xx_mcbsp_pdata,
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OMAP7XX_MCBSP_COUNT);
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if (cpu_is_omap15xx())
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omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
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OMAP15XX_MCBSP_RES_SZ,
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omap15xx_mcbsp_pdata,
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OMAP15XX_MCBSP_COUNT);
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if (cpu_is_omap16xx())
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omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
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OMAP16XX_MCBSP_RES_SZ,
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omap16xx_mcbsp_pdata,
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OMAP16XX_MCBSP_COUNT);
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return 0;
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}
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arch_initcall(omap1_mcbsp_init);
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