57 lines
1.9 KiB
Plaintext
57 lines
1.9 KiB
Plaintext
Xilinx SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
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- reg: Base address and length of the register control block
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- clocks: A list of phandles for the clocks listed in clock-names
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- clock-names: Should contain the following:
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"bus_clk" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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"ref_clk" Clock source to core during PHY power down
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- resets: A list of phandles for resets listed in reset-names
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- reset-names:
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"usb_crst" USB core reset
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"usb_hibrst" USB hibernation reset
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"usb_apbrst" USB APB reset
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Optional properties for snps,dwc3:
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- dma-coherent: Enable this flag if CCI is enabled in design. Adding this
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flag configures Global SoC bus Configuration Register and
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Xilinx USB 3.0 IP - USB coherency register to enable CCI.
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- interrupt-names: Should contain the following:
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"dwc_usb3" USB gadget mode interrupts
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"otg" USB OTG mode interrupts
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"hiber" USB hibernation interrupts
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Example device node:
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usb@0 {
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#address-cells = <0x2>;
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#size-cells = <0x1>;
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compatible = "xlnx,zynqmp-dwc3";
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reg = <0x0 0xff9d0000 0x0 0x100>;
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clock-names = "bus_clk", "ref_clk";
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clocks = <&clk125>, <&clk125>;
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resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
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reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
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ranges;
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dwc3@fe200000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe200000 0x40000>;
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interrupt-names = "dwc_usb3", "otg", "hiber";
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interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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phy-names = "usb3-phy";
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dr_mode = "host";
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dma-coherent;
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};
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};
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