159 lines
5.1 KiB
YAML
159 lines
5.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SC7280 TLMM block
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maintainers:
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- Rajendra Nayak <rnayak@codeaurora.org>
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description: |
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This binding describes the Top Level Mode Multiplexer block found in the
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SC7280 platform.
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properties:
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compatible:
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const: qcom,sc7280-pinctrl
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reg:
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maxItems: 1
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interrupts:
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description: Specifies the TLMM summary IRQ
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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description:
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Specifies the PIN numbers and Flags, as defined in defined in
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include/dt-bindings/interrupt-controller/irq.h
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const: 2
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gpio-controller: true
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'#gpio-cells':
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description: Specifying the pin number and flags, as defined in
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include/dt-bindings/gpio/gpio.h
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const: 2
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gpio-ranges:
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maxItems: 1
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wakeup-parent:
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maxItems: 1
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#PIN CONFIGURATION NODES
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patternProperties:
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'-pins$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
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sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_char0, atest_char1, atest_char2,
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atest_char3, atest_usb0, atest_usb00, atest_usb01,
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atest_usb02, atest_usb03, atest_usb1, atest_usb10,
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atest_usb11, atest_usb12, atest_usb13, audio_ref,
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cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
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cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
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cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
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cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
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dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
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gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
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mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
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mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
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mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
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mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
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mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
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mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
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mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
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pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
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pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
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qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
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qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
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qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
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qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
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sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
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sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
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tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
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uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
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usb_phy, vfr_0, vfr_1, vsense_trigger ]
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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default: 2
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description:
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Selects the drive strength for the specified pins, in mA.
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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output-high: true
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output-low: true
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required:
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- pins
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- function
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sc7280-pinctrl";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 175>;
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wakeup-parent = <&pdc>;
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qup_uart5_default: qup-uart5-pins {
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pins = "gpio46", "gpio47";
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function = "qup13";
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drive-strength = <2>;
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bias-disable;
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};
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};
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