88 lines
2.5 KiB
Plaintext
88 lines
2.5 KiB
Plaintext
Axis ARTPEC-6 Pin Controller
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Required properties:
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- compatible: "axis,artpec6-pinctrl".
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- reg: Should contain the register physical address and length for the pin
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controller.
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A pinctrl node should contain at least one subnode representing the pinctrl
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groups available on the machine. Each subnode will list the mux function
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required and what pin group it will use. Each subnode will also configure the
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drive strength and bias pullup of the pin group. If either of these options is
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not set, its actual value will be unspecified.
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Required subnode-properties:
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- function: Function to mux.
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- groups: Name of the pin group to use for the function above.
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Available functions and groups (function: group0, group1...):
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gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
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i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
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spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
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uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
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uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
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uart5nocts
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cpuclkout: cpuclkoutgrp0
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udlclkout: udlclkoutgrp0
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i2c1: i2c1grp0
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i2c2: i2c2grp0
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i2c3: i2c3grp0
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i2s0: i2s0grp0
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i2s1: i2s1grp0
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i2srefclk: i2srefclkgrp0
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spi0: spi0grp0
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spi1: spi1grp0
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pciedebug: pciedebuggrp0
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uart0: uart0grp0, uart0grp1, uart0grp2
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uart1: uart1grp0, uart1grp1
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uart2: uart2grp0, uart2grp1, uart2grp2
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uart3: uart3grp0
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uart4: uart4grp0, uart4grp1
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uart5: uart5grp0, uart5grp1, uart5nocts
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nand: nandgrp0
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sdio0: sdio0grp0
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sdio1: sdio1grp0
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ethernet: ethernetgrp0
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Optional subnode-properties (see pinctrl-bindings.txt):
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- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3.
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- bias-pull-up
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- bias-disable
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Examples:
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pinctrl@f801d000 {
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compatible = "axis,artpec6-pinctrl";
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reg = <0xf801d000 0x400>;
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pinctrl_uart0: uart0grp {
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function = "uart0";
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groups = "uart0grp0";
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drive-strength = <4>;
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bias-pull-up;
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};
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pinctrl_uart3: uart3grp {
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function = "uart3";
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groups = "uart3grp0";
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};
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};
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uart0: uart@f8036000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8036000 0x1000>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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};
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uart3: uart@f8039000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8039000 0x1000>;
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interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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};
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