77 lines
1.6 KiB
YAML
77 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Socionext UniPhier AHCI PHY
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description: |
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This describes the deivcetree bindings for PHY interfaces built into
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AHCI controller implemented on Socionext UniPhier SoCs.
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maintainers:
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- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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properties:
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compatible:
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enum:
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- socionext,uniphier-pxs2-ahci-phy
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- socionext,uniphier-pxs3-ahci-phy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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clocks:
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maxItems: 2
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clock-names:
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oneOf:
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- items: # for PXs2
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- const: link
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- items: # for others
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- const: link
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- const: phy
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: link
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- const: phy
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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ahci-glue@65700000 {
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compatible = "socionext,uniphier-pxs3-ahci-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65700000 0x100>;
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ahci_phy: phy@10 {
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compatible = "socionext,uniphier-pxs3-ahci-phy";
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reg = <0x10 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 28>, <&sys_clk 30>;
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reset-names = "link", "phy";
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resets = <&sys_rst 28>, <&sys_rst 30>;
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};
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};
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