218 lines
8.0 KiB
YAML
218 lines
8.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/video-interfaces.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common bindings for video receiver and transmitter interface endpoints
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maintainers:
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- Sakari Ailus <sakari.ailus@linux.intel.com>
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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description: |
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Video data pipelines usually consist of external devices, e.g. camera sensors,
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controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
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video DMA engines and video data processors.
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SoC internal blocks are described by DT nodes, placed similarly to other SoC
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blocks. External devices are represented as child nodes of their respective
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bus controller nodes, e.g. I2C.
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Data interfaces on all video devices are described by their child 'port' nodes.
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Configuration of a port depends on other devices participating in the data
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transfer and is described by 'endpoint' subnodes.
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device {
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...
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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...
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endpoint@0 { ... };
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endpoint@1 { ... };
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};
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port@1 { ... };
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};
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};
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If a port can be configured to work with more than one remote device on the same
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bus, an 'endpoint' child node must be provided for each of them. If more than
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one port is present in a device node or there is more than one endpoint at a
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port, or port node needs to be associated with a selected hardware interface,
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a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
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used.
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All 'port' nodes can be grouped under optional 'ports' node, which allows to
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specify #address-cells, #size-cells properties independently for the 'port'
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and 'endpoint' nodes and any child device nodes a device might have.
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Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
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phandles. An endpoint subnode of a device contains all properties needed for
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configuration of this device for data exchange with other device. In most
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cases properties at the peer 'endpoint' nodes will be identical, however they
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might need to be different when there is any signal modifications on the bus
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between two devices, e.g. there are logic signal inverters on the lines.
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It is allowed for multiple endpoints at a port to be active simultaneously,
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where supported by a device. For example, in case where a data interface of
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a device is partitioned into multiple data busses, e.g. 16-bit input port
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divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
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and data-shift properties can be used to assign physical data lines to each
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endpoint node (logical bus).
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Documenting bindings for devices
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--------------------------------
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All required and optional bindings the device supports shall be explicitly
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documented in device DT binding documentation. This also includes port and
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endpoint nodes for the device, including unit-addresses and reg properties
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where relevant.
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allOf:
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- $ref: /schemas/graph.yaml#/$defs/endpoint-base
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properties:
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slave-mode:
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type: boolean
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description:
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Indicates that the link is run in slave mode. The default when this
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property is not specified is master mode. In the slave mode horizontal and
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vertical synchronization signals are provided to the slave device (data
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source) by the master device (data sink). In the master mode the data
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source device is also the source of the synchronization signals.
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bus-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum:
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- 1 # MIPI CSI-2 C-PHY
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- 2 # MIPI CSI1
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- 3 # CCP2
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- 4 # MIPI CSI-2 D-PHY
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- 5 # Parallel
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- 6 # BT.656
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description:
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Data bus type.
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bus-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 64
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description:
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Number of data lines actively used, valid for the parallel busses.
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data-shift:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 64
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description:
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On the parallel data busses, if bus-width is used to specify the number of
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data lines, data-shift can be used to specify which data lines are used,
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e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
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hsync-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
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vsync-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. Note,
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that if HSYNC and VSYNC polarities are not specified, embedded
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synchronization may be required, where supported.
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data-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Similar to HSYNC and VSYNC, specifies data line polarity.
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data-enable-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Similar to HSYNC and VSYNC, specifies the data enable signal polarity.
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field-even-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Field signal level during the even field data transmission.
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pclk-sample:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Sample data on rising (1) or falling (0) edge of the pixel clock signal.
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sync-on-green-active:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively.
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data-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 8
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items:
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# Assume up to 9 physical lane indices
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maximum: 8
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description:
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An array of physical data lane indexes. Position of an entry determines
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the logical lane number, while the value of an entry indicates physical
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lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
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assuming the clock lane is on hardware lane 0. If the hardware does not
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support lane reordering, monotonically incremented values shall be used
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from 0 or 1 onwards, depending on whether or not there is also a clock
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lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
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clock-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32
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# Assume up to 9 physical lane indices
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maximum: 8
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description:
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Physical clock lane index. Position of an entry determines the logical
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lane number, while the value of an entry indicates physical lane, e.g. for
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a MIPI CSI-2 bus we could have "clock-lanes = <0>;", which places the
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clock lane on hardware lane 0. This property is valid for serial busses
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only (e.g. MIPI CSI-2).
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clock-noncontinuous:
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type: boolean
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description:
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Allow MIPI CSI-2 non-continuous clock mode.
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link-frequencies:
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$ref: /schemas/types.yaml#/definitions/uint64-array
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description:
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Allowed data bus frequencies. For MIPI CSI-2, for instance, this is the
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actual frequency of the bus, not bits per clock per lane value. An array
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of 64-bit unsigned integers.
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lane-polarities:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 9
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items:
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enum: [ 0, 1 ]
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description:
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An array of polarities of the lanes starting from the clock lane and
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followed by the data lanes in the same order as in data-lanes. Valid
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values are 0 (normal) and 1 (inverted). The length of the array should be
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the combined length of data-lanes and clock-lanes properties. If the
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lane-polarities property is omitted, the value must be interpreted as 0
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(normal). This property is valid for serial busses only.
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strobe:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 1 ]
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description:
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Whether the clock signal is used as clock (0) or strobe (1). Used with
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CCP2, for instance.
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additionalProperties: true
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