102 lines
2.7 KiB
YAML
102 lines
2.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Generic i.MX bus frequency device
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maintainers:
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- Leonard Crestez <leonard.crestez@nxp.com>
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description: |
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The i.MX SoC family has multiple buses for which clock frequency (and
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sometimes voltage) can be adjusted.
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Some of those buses expose register areas mentioned in the memory maps as GPV
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("Global Programmers View") but not all. Access to this area might be denied
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for normal (non-secure) world.
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The buses are based on externally licensed IPs such as ARM NIC-301 and
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Arteris FlexNOC but DT bindings are specific to the integration of these bus
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interconnect IPs into imx SOCs.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,imx8mn-nic
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- fsl,imx8mm-nic
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- fsl,imx8mq-nic
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- const: fsl,imx8m-nic
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- items:
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- enum:
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- fsl,imx8mn-noc
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- fsl,imx8mm-noc
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- fsl,imx8mq-noc
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- const: fsl,imx8m-noc
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- const: fsl,imx8m-nic
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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operating-points-v2: true
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opp-table: true
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fsl,ddrc:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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description:
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Phandle to DDR Controller.
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'#interconnect-cells':
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description:
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If specified then also act as an interconnect provider. Should only be
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set once per soc on the main noc.
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const: 1
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required:
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- compatible
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/interconnect/imx8mm.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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noc: interconnect@32700000 {
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compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
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reg = <0x32700000 0x100000>;
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clocks = <&clk IMX8MM_CLK_NOC>;
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#interconnect-cells = <1>;
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fsl,ddrc = <&ddrc>;
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operating-points-v2 = <&noc_opp_table>;
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noc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-133333333 {
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opp-hz = /bits/ 64 <133333333>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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};
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};
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};
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ddrc: memory-controller@3d400000 {
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compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
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reg = <0x3d400000 0x400000>;
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clock-names = "core", "pll", "alt", "apb";
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clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
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<&clk IMX8MM_DRAM_PLL>,
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<&clk IMX8MM_CLK_DRAM_ALT>,
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<&clk IMX8MM_CLK_DRAM_APB>;
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};
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