122 lines
3.7 KiB
YAML
122 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules
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maintainers:
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- A.s. Dong <aisheng.dong@nxp.com>
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description: |
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i.MX7ULP Clock functions are under joint control of the System
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Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
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modules, and Core Mode Controller (CMC)1 blocks
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The clocking scheme provides clear separation between M4 domain
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and A7 domain. Except for a few clock sources shared between two
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domains, such as the System Oscillator clock, the Slow IRC (SIRC),
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and and the Fast IRC clock (FIRCLK), clock sources and clock
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management are separated and contained within each domain.
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M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
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A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
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Note: this binding doc is only for A7 clock domain.
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The Peripheral Clock Control (PCC) is responsible for clock selection,
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optional division and clock gating mode for peripherals in their
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respected power domain.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
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i.MX7ULP clock IDs of each module.
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properties:
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compatible:
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enum:
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- fsl,imx7ulp-pcc2
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- fsl,imx7ulp-pcc3
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: nic1 bus clock
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- description: nic1 clock
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- description: ddr clock
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- description: apll pfd2
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- description: apll pfd1
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- description: apll pfd0
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- description: usb pll
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- description: system osc bus clock
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- description: fast internal reference clock bus
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- description: rtc osc
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- description: system pll bus clock
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clock-names:
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items:
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- const: nic1_bus_clk
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- const: nic1_clk
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- const: ddr_clk
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- const: apll_pfd2
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- const: apll_pfd1
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- const: apll_pfd0
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- const: upll
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- const: sosc_bus_clk
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- const: firc_bus_clk
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- const: rosc
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- const: spll_bus_clk
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required:
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- compatible
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- reg
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- '#clock-cells'
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx7ulp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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clock-controller@403f0000 {
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compatible = "fsl,imx7ulp-pcc2";
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reg = <0x403f0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&scg1 IMX7ULP_CLK_DDR_DIV>,
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<&scg1 IMX7ULP_CLK_APLL_PFD2>,
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<&scg1 IMX7ULP_CLK_APLL_PFD1>,
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<&scg1 IMX7ULP_CLK_APLL_PFD0>,
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<&scg1 IMX7ULP_CLK_UPLL>,
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<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_ROSC>,
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<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
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clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
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"apll_pfd2", "apll_pfd1", "apll_pfd0",
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"upll", "sosc_bus_clk", "firc_bus_clk",
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"rosc", "spll_bus_clk";
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};
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mmc@40380000 {
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compatible = "fsl,imx7ulp-usdhc";
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reg = <0x40380000 0x10000>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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bus-width = <4>;
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};
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