271 lines
7.6 KiB
Plaintext
271 lines
7.6 KiB
Plaintext
NXP i.MX System Controller Firmware (SCFW)
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--------------------------------------------------------------------
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The System Controller Firmware (SCFW) is a low-level system function
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which runs on a dedicated Cortex-M core to provide power, clock, and
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resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
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(QM, QP), and i.MX8QX (QXP, DX).
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The AP communicates with the SC using a multi-ported MU module found
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in the LSIO subsystem. The current definition of this MU module provides
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5 remote AP connections to the SC to support up to 5 execution environments
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(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
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with the LSIO DSC IP bus. The SC firmware will communicate with this MU
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using the MSI bus.
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System Controller Device Node:
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============================================================
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The scu node with the following properties shall be under the /firmware/ node.
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Required properties:
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-------------------
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- compatible: should be "fsl,imx-scu".
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- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3";
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include "gip3" if want to support general MU interrupt.
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- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
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rx, and 1 optional MU channel for general interrupt.
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All MU channels must be in the same MU instance.
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Cross instances are not allowed. The MU instance can only
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be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
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to make sure use the one which is not conflict with other
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execution environments. e.g. ATF.
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Note:
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Channel 0 must be "tx0" or "rx0".
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Channel 1 must be "tx1" or "rx1".
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Channel 2 must be "tx2" or "rx2".
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Channel 3 must be "tx3" or "rx3".
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General interrupt rx channel must be "gip3".
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e.g.
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3
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&lsio_mu1 3 3>;
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See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
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for detailed mailbox binding.
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Note: Each mu which supports general interrupt should have an alias correctly
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numbered in "aliases" node.
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e.g.
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aliases {
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mu1 = &lsio_mu1;
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};
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i.MX SCU Client Device Node:
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============================================================
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Client nodes are maintained as children of the relevant IMX-SCU device node.
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Power domain bindings based on SCU Message Protocol
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------------------------------------------------------------
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This binding for the SCU power domain providers uses the generic power
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domain binding[2].
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-scu-pd",
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"fsl,imx8qxp-scu-pd"
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followed by "fsl,scu-pd"
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- #power-domain-cells: Must be 1. Contains the Resource ID used by
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SCU commands.
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See detailed Resource ID list from:
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include/dt-bindings/firmware/imx/rsrc.h
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Clock bindings based on SCU Message Protocol
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------------------------------------------------------------
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This binding uses the common clock binding[1].
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-clk"
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"fsl,imx8qxp-clk"
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followed by "fsl,scu-clk"
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- #clock-cells: Should be 2.
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Contains the Resource and Clock ID value.
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- clocks: List of clock specifiers, must contain an entry for
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each required entry in clock-names
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- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See the full list of clock IDs from:
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include/dt-bindings/clock/imx8qxp-clock.h
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Pinctrl bindings based on SCU Message Protocol
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------------------------------------------------------------
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This binding uses the i.MX common pinctrl binding[3].
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-iomuxc",
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"fsl,imx8qxp-iomuxc",
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"fsl,imx8dxl-iomuxc".
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Required properties for Pinctrl sub nodes:
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- fsl,pins: Each entry consists of 3 integers which represents
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the mux and config setting for one pin. The first 2
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integers <pin_id mux_mode> are specified using a
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PIN_FUNC_ID macro, which can be found in
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<dt-bindings/pinctrl/pads-imx8qm.h>,
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<dt-bindings/pinctrl/pads-imx8qxp.h>,
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<dt-bindings/pinctrl/pads-imx8dxl.h>.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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Please refer to i.MX8QXP Reference Manual for detailed
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CONFIG settings.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/power/power-domain.yaml
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[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
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RTC bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: should be "fsl,imx8qxp-sc-rtc";
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OCOTP bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qm-scu-ocotp",
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"fsl,imx8qxp-scu-ocotp".
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- #address-cells: Must be 1. Contains byte index
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- #size-cells: Must be 1. Contains byte length
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Optional Child nodes:
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- Data cells of ocotp:
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Detailed bindings are described in bindings/nvmem/nvmem.txt
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Watchdog bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: should be:
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"fsl,imx8qxp-sc-wdt"
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followed by "fsl,imx-sc-wdt";
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Optional properties:
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- timeout-sec: contains the watchdog timeout in seconds.
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SCU key bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: should be:
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"fsl,imx8qxp-sc-key"
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followed by "fsl,imx-sc-key";
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- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
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Thermal bindings based on SCU Message Protocol
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------------------------------------------------------------
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Required properties:
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- compatible: Should be :
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"fsl,imx8qxp-sc-thermal"
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followed by "fsl,imx-sc-thermal";
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- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
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for a description.
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Example (imx8qxp):
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-------------
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aliases {
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mu1 = &lsio_mu1;
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};
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lsio_mu1: mailbox@5d1c0000 {
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...
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#mbox-cells = <2>;
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};
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firmware {
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scu {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0", "tx1", "tx2", "tx3",
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"rx0", "rx1", "rx2", "rx3",
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"gip3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 0 1
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&lsio_mu1 0 2
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&lsio_mu1 0 3
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&lsio_mu1 1 0
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&lsio_mu1 1 1
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&lsio_mu1 1 2
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&lsio_mu1 1 3
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&lsio_mu1 3 3>;
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clk: clk {
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compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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};
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iomuxc {
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compatible = "fsl,imx8qxp-iomuxc";
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
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SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
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>;
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};
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...
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};
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ocotp: imx8qx-ocotp {
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compatible = "fsl,imx8qxp-scu-ocotp";
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#address-cells = <1>;
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#size-cells = <1>;
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fec_mac0: mac@2c4 {
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reg = <0x2c4 8>;
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};
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};
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pd: imx8qx-pd {
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compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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rtc: rtc {
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compatible = "fsl,imx8qxp-sc-rtc";
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};
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scu_key: scu-key {
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compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
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linux,keycodes = <KEY_POWER>;
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};
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watchdog {
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compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
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timeout-sec = <60>;
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};
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tsens: thermal-sensor {
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compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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};
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serial@5a060000 {
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...
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
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clock-names = "ipg";
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power-domains = <&pd IMX_SC_R_UART_0>;
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};
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