153 lines
3.6 KiB
C
153 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2012 Alexandre Pereira da Silva <aletes.xgr@gmail.com>
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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struct lpc32xx_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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};
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#define PWM_ENABLE BIT(31)
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#define PWM_PIN_LEVEL BIT(30)
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#define to_lpc32xx_pwm_chip(_chip) \
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container_of(_chip, struct lpc32xx_pwm_chip, chip)
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static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
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unsigned long long c;
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int period_cycles, duty_cycles;
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u32 val;
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c = clk_get_rate(lpc32xx->clk);
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/* The highest acceptable divisor is 256, which is represented by 0 */
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period_cycles = div64_u64(c * period_ns,
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(unsigned long long)NSEC_PER_SEC * 256);
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if (!period_cycles || period_cycles > 256)
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return -ERANGE;
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if (period_cycles == 256)
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period_cycles = 0;
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/* Compute 256 x #duty/period value and care for corner cases */
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duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256,
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period_ns);
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if (!duty_cycles)
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duty_cycles = 1;
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if (duty_cycles > 255)
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duty_cycles = 255;
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val = readl(lpc32xx->base);
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val &= ~0xFFFF;
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val |= (period_cycles << 8) | duty_cycles;
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writel(val, lpc32xx->base);
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return 0;
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}
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static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
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u32 val;
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int ret;
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ret = clk_prepare_enable(lpc32xx->clk);
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if (ret)
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return ret;
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val = readl(lpc32xx->base);
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val |= PWM_ENABLE;
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writel(val, lpc32xx->base);
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return 0;
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}
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static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip);
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u32 val;
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val = readl(lpc32xx->base);
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val &= ~PWM_ENABLE;
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writel(val, lpc32xx->base);
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clk_disable_unprepare(lpc32xx->clk);
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}
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static const struct pwm_ops lpc32xx_pwm_ops = {
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.config = lpc32xx_pwm_config,
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.enable = lpc32xx_pwm_enable,
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.disable = lpc32xx_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int lpc32xx_pwm_probe(struct platform_device *pdev)
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{
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struct lpc32xx_pwm_chip *lpc32xx;
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int ret;
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u32 val;
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lpc32xx = devm_kzalloc(&pdev->dev, sizeof(*lpc32xx), GFP_KERNEL);
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if (!lpc32xx)
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return -ENOMEM;
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lpc32xx->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(lpc32xx->base))
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return PTR_ERR(lpc32xx->base);
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lpc32xx->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(lpc32xx->clk))
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return PTR_ERR(lpc32xx->clk);
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lpc32xx->chip.dev = &pdev->dev;
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lpc32xx->chip.ops = &lpc32xx_pwm_ops;
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lpc32xx->chip.npwm = 1;
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/* If PWM is disabled, configure the output to the default value */
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val = readl(lpc32xx->base);
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val &= ~PWM_PIN_LEVEL;
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writel(val, lpc32xx->base);
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ret = devm_pwmchip_add(&pdev->dev, &lpc32xx->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip, error %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct of_device_id lpc32xx_pwm_dt_ids[] = {
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{ .compatible = "nxp,lpc3220-pwm", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, lpc32xx_pwm_dt_ids);
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static struct platform_driver lpc32xx_pwm_driver = {
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.driver = {
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.name = "lpc32xx-pwm",
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.of_match_table = lpc32xx_pwm_dt_ids,
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},
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.probe = lpc32xx_pwm_probe,
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};
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module_platform_driver(lpc32xx_pwm_driver);
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MODULE_ALIAS("platform:lpc32xx-pwm");
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MODULE_AUTHOR("Alexandre Pereira da Silva <aletes.xgr@gmail.com>");
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MODULE_DESCRIPTION("LPC32XX PWM Driver");
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MODULE_LICENSE("GPL v2");
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