406 lines
13 KiB
C
406 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* camss-csiphy-3ph-1-0.c
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*
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* Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0
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*
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* Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
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* Copyright (C) 2016-2018 Linaro Ltd.
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*/
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#include "camss.h"
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#include "camss-csiphy.h"
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6))
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#define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3)
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#define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4
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#define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5
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#define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02
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#define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50
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#define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa
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#define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2)
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#define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0)
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#define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2
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#define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0)
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#define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1)
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#define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1
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#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n))
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#define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n))
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0)
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#define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1)
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#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n))
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#define CSIPHY_DEFAULT_PARAMS 0
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#define CSIPHY_LANE_ENABLE 1
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#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2
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#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3
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#define CSIPHY_DNP_PARAMS 4
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#define CSIPHY_2PH_REGS 5
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#define CSIPHY_3PH_REGS 6
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struct csiphy_reg_t {
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s32 reg_addr;
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s32 reg_data;
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s32 delay;
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u32 csiphy_param_type;
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};
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static const struct
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csiphy_reg_t lane_regs_sdm845[5][14] = {
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{
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{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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{
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{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
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{0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
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{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
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{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
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},
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};
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static void csiphy_hw_version_read(struct csiphy_device *csiphy,
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struct device *dev)
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{
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u32 hw_version;
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writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID,
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csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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hw_version = readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12));
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8;
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16;
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hw_version |= readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24;
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dev_err(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version);
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}
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/*
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* csiphy_reset - Perform software reset on CSIPHY module
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* @csiphy: CSIPHY device
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*/
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static void csiphy_reset(struct csiphy_device *csiphy)
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{
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writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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usleep_range(5000, 8000);
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writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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}
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static irqreturn_t csiphy_isr(int irq, void *dev)
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{
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struct csiphy_device *csiphy = dev;
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int i;
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for (i = 0; i < 11; i++) {
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int c = i + 22;
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u8 val = readl_relaxed(csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i));
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writel_relaxed(val, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c));
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}
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writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
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writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10));
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for (i = 22; i < 33; i++)
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writel_relaxed(0x0, csiphy->base +
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CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i));
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return IRQ_HANDLED;
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}
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/*
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* csiphy_settle_cnt_calc - Calculate settle count value
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*
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* Helper function to calculate settle count value. This is
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* based on the CSI2 T_hs_settle parameter which in turn
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* is calculated based on the CSI2 transmitter link frequency.
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*
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* Return settle count value or 0 if the CSI2 link frequency
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* is not available
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*/
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static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)
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{
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u32 ui; /* ps */
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u32 timer_period; /* ps */
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u32 t_hs_prepare_max; /* ps */
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u32 t_hs_settle; /* ps */
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u8 settle_cnt;
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if (link_freq <= 0)
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return 0;
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ui = div_u64(1000000000000LL, link_freq);
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ui /= 2;
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t_hs_prepare_max = 85000 + 6 * ui;
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t_hs_settle = t_hs_prepare_max;
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timer_period = div_u64(1000000000000LL, timer_clk_rate);
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settle_cnt = t_hs_settle / timer_period - 6;
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return settle_cnt;
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}
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static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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u8 settle_cnt)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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int i, l = 0;
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u8 val;
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for (i = 0; i <= c->num_data; i++) {
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if (i == c->num_data)
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l = 7;
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else
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l = c->data[i].pos * 2;
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val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
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val |= 0x17;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
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val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l));
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val = settle_cnt;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l));
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val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM |
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CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l));
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val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l));
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val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l));
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val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP |
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CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l));
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val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l));
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val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l));
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val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL;
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writel_relaxed(val, csiphy->base +
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CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l));
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}
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val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l));
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if (csiphy->camss->version == CAMSS_660)
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val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660;
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else
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val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l));
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val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l));
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}
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static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
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u8 settle_cnt)
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{
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int i, l;
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u32 val;
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for (l = 0; l < 5; l++) {
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for (i = 0; i < 14; i++) {
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const struct csiphy_reg_t *r = &lane_regs_sdm845[l][i];
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switch (r->csiphy_param_type) {
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case CSIPHY_SETTLE_CNT_LOWER_BYTE:
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val = settle_cnt & 0xff;
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break;
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case CSIPHY_DNP_PARAMS:
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continue;
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default:
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val = r->reg_data;
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break;
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}
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writel_relaxed(val, csiphy->base + r->reg_addr);
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}
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}
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}
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static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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s64 link_freq, u8 lane_mask)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val;
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int i;
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settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
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val = BIT(c->clk.pos);
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for (i = 0; i < c->num_data; i++)
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val |= BIT(c->data[i].pos * 2);
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
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val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
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val = 0x02;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(7));
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val = 0x00;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0));
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if (csiphy->camss->version == CAMSS_8x16 ||
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csiphy->camss->version == CAMSS_8x96)
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csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt);
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else if (csiphy->camss->version == CAMSS_845)
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csiphy_gen2_config_lanes(csiphy, settle_cnt);
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11));
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val = 0xff;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12));
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val = 0xfb;
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writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13));
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val = 0xff;
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|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14));
|
|
|
|
val = 0x7f;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15));
|
|
|
|
val = 0xff;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16));
|
|
|
|
val = 0xff;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17));
|
|
|
|
val = 0xef;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18));
|
|
|
|
val = 0xff;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19));
|
|
|
|
val = 0xff;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20));
|
|
|
|
val = 0xff;
|
|
writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21));
|
|
}
|
|
|
|
static void csiphy_lanes_disable(struct csiphy_device *csiphy,
|
|
struct csiphy_config *cfg)
|
|
{
|
|
writel_relaxed(0, csiphy->base +
|
|
CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5));
|
|
|
|
writel_relaxed(0, csiphy->base +
|
|
CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6));
|
|
}
|
|
|
|
const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
|
|
.hw_version_read = csiphy_hw_version_read,
|
|
.reset = csiphy_reset,
|
|
.lanes_enable = csiphy_lanes_enable,
|
|
.lanes_disable = csiphy_lanes_disable,
|
|
.isr = csiphy_isr,
|
|
};
|