125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* R-Car Gen3 HDMI PHY
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*
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* Copyright (C) 2016 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*/
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_modes.h>
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#define RCAR_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */
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#define RCAR_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */
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#define RCAR_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */
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struct rcar_hdmi_phy_params {
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unsigned long mpixelclock;
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u16 opmode_div; /* Mode of operation and PLL dividers */
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u16 curr_gmp; /* PLL current and Gmp (conductance) */
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u16 div; /* PLL dividers */
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};
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static const struct rcar_hdmi_phy_params rcar_hdmi_phy_params[] = {
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{ 35500000, 0x0003, 0x0344, 0x0328 },
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{ 44900000, 0x0003, 0x0285, 0x0128 },
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{ 71000000, 0x0002, 0x1184, 0x0314 },
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{ 90000000, 0x0002, 0x1144, 0x0114 },
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{ 140250000, 0x0001, 0x20c4, 0x030a },
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{ 182750000, 0x0001, 0x2084, 0x010a },
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{ 281250000, 0x0000, 0x0084, 0x0305 },
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{ 297000000, 0x0000, 0x0084, 0x0105 },
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{ ~0UL, 0x0000, 0x0000, 0x0000 },
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};
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static enum drm_mode_status
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rcar_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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/*
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* The maximum supported clock frequency is 297 MHz, as shown in the PHY
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* parameters table.
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*/
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if (mode->clock > 297000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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static int rcar_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data,
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unsigned long mpixelclock)
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{
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const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params;
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for (; params->mpixelclock != ~0UL; ++params) {
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if (mpixelclock <= params->mpixelclock)
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break;
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}
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if (params->mpixelclock == ~0UL)
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return -EINVAL;
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dw_hdmi_phy_i2c_write(hdmi, params->opmode_div,
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RCAR_HDMI_PHY_OPMODE_PLLCFG);
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dw_hdmi_phy_i2c_write(hdmi, params->curr_gmp,
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RCAR_HDMI_PHY_PLLCURRGMPCTRL);
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dw_hdmi_phy_i2c_write(hdmi, params->div, RCAR_HDMI_PHY_PLLDIVCTRL);
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return 0;
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}
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static const struct dw_hdmi_plat_data rcar_dw_hdmi_plat_data = {
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.output_port = 1,
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.mode_valid = rcar_hdmi_mode_valid,
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.configure_phy = rcar_hdmi_phy_configure,
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};
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static int rcar_dw_hdmi_probe(struct platform_device *pdev)
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{
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struct dw_hdmi *hdmi;
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hdmi = dw_hdmi_probe(pdev, &rcar_dw_hdmi_plat_data);
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if (IS_ERR(hdmi))
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return PTR_ERR(hdmi);
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platform_set_drvdata(pdev, hdmi);
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return 0;
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}
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static int rcar_dw_hdmi_remove(struct platform_device *pdev)
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{
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struct dw_hdmi *hdmi = platform_get_drvdata(pdev);
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dw_hdmi_remove(hdmi);
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return 0;
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}
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static const struct of_device_id rcar_dw_hdmi_of_table[] = {
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{ .compatible = "renesas,rcar-gen3-hdmi" },
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{ /* Sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, rcar_dw_hdmi_of_table);
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static struct platform_driver rcar_dw_hdmi_platform_driver = {
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.probe = rcar_dw_hdmi_probe,
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.remove = rcar_dw_hdmi_remove,
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.driver = {
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.name = "rcar-dw-hdmi",
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.of_match_table = rcar_dw_hdmi_of_table,
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},
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};
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module_platform_driver(rcar_dw_hdmi_platform_driver);
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MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
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MODULE_DESCRIPTION("Renesas R-Car Gen3 HDMI Encoder Driver");
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MODULE_LICENSE("GPL");
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