454 lines
14 KiB
C
454 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include "hdmi.h"
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struct hdmi_pll_8960 {
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struct platform_device *pdev;
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struct clk_hw clk_hw;
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void __iomem *mmio;
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unsigned long pixclk;
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};
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#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8960, clk_hw)
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/*
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* HDMI PLL:
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*
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* To get the parent clock setup properly, we need to plug in hdmi pll
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* configuration into common-clock-framework.
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*/
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struct pll_rate {
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unsigned long rate;
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int num_reg;
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struct {
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u32 val;
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u32 reg;
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} conf[32];
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};
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/* NOTE: keep sorted highest freq to lowest: */
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static const struct pll_rate freqtbl[] = {
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{ 154000000, 14, {
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{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4d, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x5e, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x42, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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}
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},
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/* 1080p60/1080p50 case */
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{ 148500000, 27, {
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{ 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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}
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},
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{ 108000000, 13, {
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{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x21, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x1c, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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}
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},
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/* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */
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{ 74250000, 8, {
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x12, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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}
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},
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{ 74176000, 14, {
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{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0xe5, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x0c, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x7d, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xbc, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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}
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},
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{ 65000000, 14, {
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{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x8a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x0b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4b, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x09, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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}
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},
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/* 480p60/480i60 */
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{ 27030000, 18, {
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x38, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xff, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4e, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0xd7, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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}
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},
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/* 576p50/576i50 */
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{ 27000000, 27, {
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{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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}
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},
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/* 640x480p60 */
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{ 25200000, 27, {
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{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x77, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x20, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0xf4, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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}
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},
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};
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static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
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{
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msm_writel(data, pll->mmio + reg);
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}
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static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
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{
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return msm_readl(pll->mmio + reg);
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}
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static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
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{
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return platform_get_drvdata(pll->pdev);
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}
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static int hdmi_pll_enable(struct clk_hw *hw)
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{
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struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
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struct hdmi_phy *phy = pll_get_phy(pll);
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int timeout_count, pll_lock_retry = 10;
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unsigned int val;
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DBG("");
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/* Assert PLL S/W reset */
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10);
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a);
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/* Wait for a short time before de-asserting
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* to allow the hardware to complete its job.
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* This much of delay should be fine for hardware
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* to assert and de-assert.
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*/
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udelay(10);
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/* De-assert PLL S/W reset */
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
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val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
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val |= HDMI_8960_PHY_REG12_SW_RESET;
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/* Assert PHY S/W reset */
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
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val &= ~HDMI_8960_PHY_REG12_SW_RESET;
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/*
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* Wait for a short time before de-asserting to allow the hardware to
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* complete its job. This much of delay should be fine for hardware to
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* assert and de-assert.
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*/
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udelay(10);
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/* De-assert PHY S/W reset */
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x3f);
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val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
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val |= HDMI_8960_PHY_REG12_PWRDN_B;
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
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/* Wait 10 us for enabling global power for PHY */
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mb();
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udelay(10);
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val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
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val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B;
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val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL;
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pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG2, 0x80);
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timeout_count = 1000;
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while (--pll_lock_retry > 0) {
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/* are we there yet? */
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val = pll_read(pll, REG_HDMI_8960_PHY_PLL_STATUS0);
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if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK)
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break;
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udelay(1);
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if (--timeout_count > 0)
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continue;
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/*
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* PLL has still not locked.
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* Do a software reset and try again
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* Assert PLL S/W reset first
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*/
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
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udelay(10);
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pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
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/*
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* Wait for a short duration for the PLL calibration
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* before checking if the PLL gets locked
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*/
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udelay(350);
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timeout_count = 1000;
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}
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return 0;
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}
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static void hdmi_pll_disable(struct clk_hw *hw)
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{
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struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
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struct hdmi_phy *phy = pll_get_phy(pll);
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unsigned int val;
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DBG("");
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val = hdmi_phy_read(phy, REG_HDMI_8960_PHY_REG12);
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val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
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hdmi_phy_write(phy, REG_HDMI_8960_PHY_REG12, val);
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|
|
|
val = pll_read(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B);
|
|
val |= HDMI_8960_PHY_REG12_SW_RESET;
|
|
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
|
|
pll_write(pll, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
|
|
/* Make sure HDMI PHY/PLL are powered down */
|
|
mb();
|
|
}
|
|
|
|
static const struct pll_rate *find_rate(unsigned long rate)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1; i < ARRAY_SIZE(freqtbl); i++)
|
|
if (rate > freqtbl[i].rate)
|
|
return &freqtbl[i - 1];
|
|
|
|
return &freqtbl[i - 1];
|
|
}
|
|
|
|
static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
|
|
|
|
return pll->pixclk;
|
|
}
|
|
|
|
static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *parent_rate)
|
|
{
|
|
const struct pll_rate *pll_rate = find_rate(rate);
|
|
|
|
return pll_rate->rate;
|
|
}
|
|
|
|
static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);
|
|
const struct pll_rate *pll_rate = find_rate(rate);
|
|
int i;
|
|
|
|
DBG("rate=%lu", rate);
|
|
|
|
for (i = 0; i < pll_rate->num_reg; i++)
|
|
pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val);
|
|
|
|
pll->pixclk = rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct clk_ops hdmi_pll_ops = {
|
|
.enable = hdmi_pll_enable,
|
|
.disable = hdmi_pll_disable,
|
|
.recalc_rate = hdmi_pll_recalc_rate,
|
|
.round_rate = hdmi_pll_round_rate,
|
|
.set_rate = hdmi_pll_set_rate,
|
|
};
|
|
|
|
static const char * const hdmi_pll_parents[] = {
|
|
"pxo",
|
|
};
|
|
|
|
static struct clk_init_data pll_init = {
|
|
.name = "hdmi_pll",
|
|
.ops = &hdmi_pll_ops,
|
|
.parent_names = hdmi_pll_parents,
|
|
.num_parents = ARRAY_SIZE(hdmi_pll_parents),
|
|
.flags = CLK_IGNORE_UNUSED,
|
|
};
|
|
|
|
int msm_hdmi_pll_8960_init(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct hdmi_pll_8960 *pll;
|
|
struct clk *clk;
|
|
int i;
|
|
|
|
/* sanity check: */
|
|
for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++)
|
|
if (WARN_ON(freqtbl[i].rate < freqtbl[i + 1].rate))
|
|
return -EINVAL;
|
|
|
|
pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
|
|
if (!pll)
|
|
return -ENOMEM;
|
|
|
|
pll->mmio = msm_ioremap(pdev, "hdmi_pll", "HDMI_PLL");
|
|
if (IS_ERR(pll->mmio)) {
|
|
DRM_DEV_ERROR(dev, "failed to map pll base\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pll->pdev = pdev;
|
|
pll->clk_hw.init = &pll_init;
|
|
|
|
clk = devm_clk_register(dev, &pll->clk_hw);
|
|
if (IS_ERR(clk)) {
|
|
DRM_DEV_ERROR(dev, "failed to register pll clock\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|