409 lines
10 KiB
C
409 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_SSPP_H
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#define _DPU_HW_SSPP_H
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_util.h"
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#include "dpu_hw_blk.h"
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#include "dpu_formats.h"
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struct dpu_hw_pipe;
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/**
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* Flags
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*/
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#define DPU_SSPP_FLIP_LR BIT(0)
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#define DPU_SSPP_FLIP_UD BIT(1)
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#define DPU_SSPP_SOURCE_ROTATED_90 BIT(2)
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#define DPU_SSPP_ROT_90 BIT(3)
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#define DPU_SSPP_SOLID_FILL BIT(4)
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/**
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* Define all scaler feature bits in catalog
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*/
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#define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \
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(1UL << DPU_SSPP_SCALER_QSEED2) | \
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(1UL << DPU_SSPP_SCALER_QSEED3) | \
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(1UL << DPU_SSPP_SCALER_QSEED3LITE) | \
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(1UL << DPU_SSPP_SCALER_QSEED4))
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/**
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* Component indices
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*/
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enum {
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DPU_SSPP_COMP_0,
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DPU_SSPP_COMP_1_2,
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DPU_SSPP_COMP_2,
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DPU_SSPP_COMP_3,
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DPU_SSPP_COMP_MAX
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};
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/**
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* DPU_SSPP_RECT_SOLO - multirect disabled
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* DPU_SSPP_RECT_0 - rect0 of a multirect pipe
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* DPU_SSPP_RECT_1 - rect1 of a multirect pipe
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*
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* Note: HW supports multirect with either RECT0 or
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* RECT1. Considering no benefit of such configs over
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* SOLO mode and to keep the plane management simple,
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* we dont support single rect multirect configs.
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*/
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enum dpu_sspp_multirect_index {
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DPU_SSPP_RECT_SOLO = 0,
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DPU_SSPP_RECT_0,
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DPU_SSPP_RECT_1,
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};
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enum dpu_sspp_multirect_mode {
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DPU_SSPP_MULTIRECT_NONE = 0,
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DPU_SSPP_MULTIRECT_PARALLEL,
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DPU_SSPP_MULTIRECT_TIME_MX,
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};
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enum {
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DPU_FRAME_LINEAR,
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DPU_FRAME_TILE_A4X,
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DPU_FRAME_TILE_A5X,
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};
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enum dpu_hw_filter {
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DPU_SCALE_FILTER_NEAREST = 0,
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DPU_SCALE_FILTER_BIL,
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DPU_SCALE_FILTER_PCMN,
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DPU_SCALE_FILTER_CA,
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DPU_SCALE_FILTER_MAX
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};
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enum dpu_hw_filter_alpa {
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DPU_SCALE_ALPHA_PIXEL_REP,
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DPU_SCALE_ALPHA_BIL
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};
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enum dpu_hw_filter_yuv {
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DPU_SCALE_2D_4X4,
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DPU_SCALE_2D_CIR,
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DPU_SCALE_1D_SEP,
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DPU_SCALE_BIL
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};
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struct dpu_hw_sharp_cfg {
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u32 strength;
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u32 edge_thr;
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u32 smooth_thr;
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u32 noise_thr;
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};
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struct dpu_hw_pixel_ext {
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/* scaling factors are enabled for this input layer */
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uint8_t enable_pxl_ext;
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int init_phase_x[DPU_MAX_PLANES];
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int phase_step_x[DPU_MAX_PLANES];
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int init_phase_y[DPU_MAX_PLANES];
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int phase_step_y[DPU_MAX_PLANES];
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/*
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* Number of pixels extension in left, right, top and bottom direction
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* for all color components. This pixel value for each color component
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* should be sum of fetch + repeat pixels.
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*/
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int num_ext_pxls_left[DPU_MAX_PLANES];
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int num_ext_pxls_right[DPU_MAX_PLANES];
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int num_ext_pxls_top[DPU_MAX_PLANES];
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int num_ext_pxls_btm[DPU_MAX_PLANES];
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/*
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* Number of pixels needs to be overfetched in left, right, top and
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* bottom directions from source image for scaling.
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*/
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int left_ftch[DPU_MAX_PLANES];
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int right_ftch[DPU_MAX_PLANES];
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int top_ftch[DPU_MAX_PLANES];
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int btm_ftch[DPU_MAX_PLANES];
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/*
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* Number of pixels needs to be repeated in left, right, top and
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* bottom directions for scaling.
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*/
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int left_rpt[DPU_MAX_PLANES];
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int right_rpt[DPU_MAX_PLANES];
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int top_rpt[DPU_MAX_PLANES];
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int btm_rpt[DPU_MAX_PLANES];
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uint32_t roi_w[DPU_MAX_PLANES];
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uint32_t roi_h[DPU_MAX_PLANES];
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/*
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* Filter type to be used for scaling in horizontal and vertical
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* directions
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*/
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enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
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enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
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};
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/**
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* struct dpu_hw_pipe_cfg : Pipe description
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* @layout: format layout information for programming buffer to hardware
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* @src_rect: src ROI, caller takes into account the different operations
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* such as decimation, flip etc to program this field
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* @dest_rect: destination ROI.
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* @index: index of the rectangle of SSPP
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* @mode: parallel or time multiplex multirect mode
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*/
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struct dpu_hw_pipe_cfg {
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struct dpu_hw_fmt_layout layout;
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struct drm_rect src_rect;
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struct drm_rect dst_rect;
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enum dpu_sspp_multirect_index index;
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enum dpu_sspp_multirect_mode mode;
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};
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/**
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* struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration
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* @danger_lut: LUT for generate danger level based on fill level
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* @safe_lut: LUT for generate safe level based on fill level
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* @creq_lut: LUT for generate creq level based on fill level
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* @creq_vblank: creq value generated to vbif during vertical blanking
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* @danger_vblank: danger value generated during vertical blanking
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* @vblank_en: enable creq_vblank and danger_vblank during vblank
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* @danger_safe_en: enable danger safe generation
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*/
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struct dpu_hw_pipe_qos_cfg {
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u32 danger_lut;
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u32 safe_lut;
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u64 creq_lut;
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u32 creq_vblank;
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u32 danger_vblank;
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bool vblank_en;
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bool danger_safe_en;
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};
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/**
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* enum CDP preload ahead address size
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*/
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enum {
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DPU_SSPP_CDP_PRELOAD_AHEAD_32,
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DPU_SSPP_CDP_PRELOAD_AHEAD_64
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};
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/**
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* struct dpu_hw_pipe_cdp_cfg : CDP configuration
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* @enable: true to enable CDP
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* @ubwc_meta_enable: true to enable ubwc metadata preload
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* @tile_amortize_enable: true to enable amortization control for tile format
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* @preload_ahead: number of request to preload ahead
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* DPU_SSPP_CDP_PRELOAD_AHEAD_32,
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* DPU_SSPP_CDP_PRELOAD_AHEAD_64
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*/
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struct dpu_hw_pipe_cdp_cfg {
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bool enable;
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bool ubwc_meta_enable;
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bool tile_amortize_enable;
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u32 preload_ahead;
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};
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/**
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* struct dpu_hw_pipe_ts_cfg - traffic shaper configuration
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* @size: size to prefill in bytes, or zero to disable
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* @time: time to prefill in usec, or zero to disable
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*/
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struct dpu_hw_pipe_ts_cfg {
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u64 size;
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u64 time;
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};
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/**
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* struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions
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* Caller must call the init function to get the pipe context for each pipe
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct dpu_hw_sspp_ops {
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/**
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* setup_format - setup pixel format cropping rectangle, flip
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe config structure
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* @flags: Extra flags for format config
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* @index: rectangle index in multirect
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*/
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void (*setup_format)(struct dpu_hw_pipe *ctx,
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const struct dpu_format *fmt, u32 flags,
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enum dpu_sspp_multirect_index index);
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/**
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* setup_rects - setup pipe ROI rectangles
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe config structure
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* @index: rectangle index in multirect
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*/
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void (*setup_rects)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_cfg *cfg,
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enum dpu_sspp_multirect_index index);
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/**
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* setup_pe - setup pipe pixel extension
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* @ctx: Pointer to pipe context
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* @pe_ext: Pointer to pixel ext settings
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*/
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void (*setup_pe)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pixel_ext *pe_ext);
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/**
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* setup_sourceaddress - setup pipe source addresses
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe config structure
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* @index: rectangle index in multirect
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*/
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void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_cfg *cfg,
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enum dpu_sspp_multirect_index index);
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/**
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* setup_csc - setup color space coversion
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* @ctx: Pointer to pipe context
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* @data: Pointer to config structure
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*/
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void (*setup_csc)(struct dpu_hw_pipe *ctx, struct dpu_csc_cfg *data);
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/**
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* setup_solidfill - enable/disable colorfill
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* @ctx: Pointer to pipe context
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* @const_color: Fill color value
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* @flags: Pipe flags
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* @index: rectangle index in multirect
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*/
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void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color,
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enum dpu_sspp_multirect_index index);
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/**
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* setup_multirect - setup multirect configuration
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* @ctx: Pointer to pipe context
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* @index: rectangle index in multirect
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* @mode: parallel fetch / time multiplex multirect mode
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*/
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void (*setup_multirect)(struct dpu_hw_pipe *ctx,
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enum dpu_sspp_multirect_index index,
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enum dpu_sspp_multirect_mode mode);
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/**
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* setup_sharpening - setup sharpening
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to config structure
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*/
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void (*setup_sharpening)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_sharp_cfg *cfg);
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/**
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* setup_danger_safe_lut - setup danger safe LUTs
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*
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*/
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void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_qos_cfg *cfg);
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/**
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* setup_creq_lut - setup CREQ LUT
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*
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*/
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void (*setup_creq_lut)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_qos_cfg *cfg);
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/**
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* setup_qos_ctrl - setup QoS control
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*
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*/
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void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_qos_cfg *cfg);
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/**
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* setup_histogram - setup histograms
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to histogram configuration
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*/
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void (*setup_histogram)(struct dpu_hw_pipe *ctx,
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void *cfg);
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/**
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* setup_scaler - setup scaler
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* @ctx: Pointer to pipe context
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* @pipe_cfg: Pointer to pipe configuration
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* @pe_cfg: Pointer to pixel extension configuration
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* @scaler_cfg: Pointer to scaler configuration
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*/
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void (*setup_scaler)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_cfg *pipe_cfg,
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struct dpu_hw_pixel_ext *pe_cfg,
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void *scaler_cfg);
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/**
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* get_scaler_ver - get scaler h/w version
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* @ctx: Pointer to pipe context
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*/
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u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx);
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/**
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* setup_cdp - setup client driven prefetch
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to cdp configuration
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*/
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void (*setup_cdp)(struct dpu_hw_pipe *ctx,
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struct dpu_hw_pipe_cdp_cfg *cfg);
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};
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/**
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* struct dpu_hw_pipe - pipe description
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* @base: hardware block base structure
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* @hw: block hardware details
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* @catalog: back pointer to catalog
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* @mdp: pointer to associated mdp portion of the catalog
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* @idx: pipe index
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* @cap: pointer to layer_cfg
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* @ops: pointer to operations possible for this pipe
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*/
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struct dpu_hw_pipe {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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struct dpu_mdss_cfg *catalog;
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const struct dpu_mdp_cfg *mdp;
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/* Pipe */
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enum dpu_sspp idx;
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const struct dpu_sspp_cfg *cap;
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/* Ops */
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struct dpu_hw_sspp_ops ops;
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};
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/**
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* dpu_hw_sspp_init - initializes the sspp hw driver object.
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* Should be called once before accessing every pipe.
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* @idx: Pipe index for which driver object is required
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* @addr: Mapped register io address of MDP
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* @catalog : Pointer to mdss catalog data
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* @is_virtual_pipe: is this pipe virtual pipe
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*/
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struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx,
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void __iomem *addr, struct dpu_mdss_cfg *catalog,
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bool is_virtual_pipe);
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/**
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* dpu_hw_sspp_destroy(): Destroys SSPP driver context
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* should be called during Hw pipe cleanup.
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* @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init
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*/
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void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx);
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#endif /*_DPU_HW_SSPP_H */
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