420 lines
14 KiB
C
420 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Analog Devices ADV7511 HDMI transmitter driver
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*
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* Copyright 2012 Analog Devices Inc.
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*/
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#ifndef __DRM_I2C_ADV7511_H__
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#define __DRM_I2C_ADV7511_H__
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#include <linux/hdmi.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_modes.h>
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#define ADV7511_REG_CHIP_REVISION 0x00
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#define ADV7511_REG_N0 0x01
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#define ADV7511_REG_N1 0x02
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#define ADV7511_REG_N2 0x03
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#define ADV7511_REG_SPDIF_FREQ 0x04
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#define ADV7511_REG_CTS_AUTOMATIC1 0x05
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#define ADV7511_REG_CTS_AUTOMATIC2 0x06
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#define ADV7511_REG_CTS_MANUAL0 0x07
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#define ADV7511_REG_CTS_MANUAL1 0x08
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#define ADV7511_REG_CTS_MANUAL2 0x09
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#define ADV7511_REG_AUDIO_SOURCE 0x0a
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#define ADV7511_REG_AUDIO_CONFIG 0x0b
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#define ADV7511_REG_I2S_CONFIG 0x0c
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#define ADV7511_REG_I2S_WIDTH 0x0d
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#define ADV7511_REG_AUDIO_SUB_SRC0 0x0e
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#define ADV7511_REG_AUDIO_SUB_SRC1 0x0f
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#define ADV7511_REG_AUDIO_SUB_SRC2 0x10
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#define ADV7511_REG_AUDIO_SUB_SRC3 0x11
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#define ADV7511_REG_AUDIO_CFG1 0x12
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#define ADV7511_REG_AUDIO_CFG2 0x13
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#define ADV7511_REG_AUDIO_CFG3 0x14
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#define ADV7511_REG_I2C_FREQ_ID_CFG 0x15
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#define ADV7511_REG_VIDEO_INPUT_CFG1 0x16
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#define ADV7511_REG_CSC_UPPER(x) (0x18 + (x) * 2)
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#define ADV7511_REG_CSC_LOWER(x) (0x19 + (x) * 2)
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#define ADV7511_REG_SYNC_DECODER(x) (0x30 + (x))
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#define ADV7511_REG_DE_GENERATOR (0x35 + (x))
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#define ADV7511_REG_PIXEL_REPETITION 0x3b
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#define ADV7511_REG_VIC_MANUAL 0x3c
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#define ADV7511_REG_VIC_SEND 0x3d
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#define ADV7511_REG_VIC_DETECTED 0x3e
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#define ADV7511_REG_AUX_VIC_DETECTED 0x3f
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#define ADV7511_REG_PACKET_ENABLE0 0x40
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#define ADV7511_REG_POWER 0x41
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#define ADV7511_REG_STATUS 0x42
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#define ADV7511_REG_EDID_I2C_ADDR 0x43
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#define ADV7511_REG_PACKET_ENABLE1 0x44
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#define ADV7511_REG_PACKET_I2C_ADDR 0x45
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#define ADV7511_REG_DSD_ENABLE 0x46
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#define ADV7511_REG_VIDEO_INPUT_CFG2 0x48
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#define ADV7511_REG_INFOFRAME_UPDATE 0x4a
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#define ADV7511_REG_GC(x) (0x4b + (x)) /* 0x4b - 0x51 */
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#define ADV7511_REG_AVI_INFOFRAME_VERSION 0x52
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#define ADV7511_REG_AVI_INFOFRAME_LENGTH 0x53
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#define ADV7511_REG_AVI_INFOFRAME_CHECKSUM 0x54
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#define ADV7511_REG_AVI_INFOFRAME(x) (0x55 + (x)) /* 0x55 - 0x6f */
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#define ADV7511_REG_AUDIO_INFOFRAME_VERSION 0x70
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#define ADV7511_REG_AUDIO_INFOFRAME_LENGTH 0x71
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#define ADV7511_REG_AUDIO_INFOFRAME_CHECKSUM 0x72
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#define ADV7511_REG_AUDIO_INFOFRAME(x) (0x73 + (x)) /* 0x73 - 0x7c */
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#define ADV7511_REG_INT_ENABLE(x) (0x94 + (x))
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#define ADV7511_REG_INT(x) (0x96 + (x))
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#define ADV7511_REG_INPUT_CLK_DIV 0x9d
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#define ADV7511_REG_PLL_STATUS 0x9e
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#define ADV7511_REG_HDMI_POWER 0xa1
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#define ADV7511_REG_HDCP_HDMI_CFG 0xaf
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#define ADV7511_REG_AN(x) (0xb0 + (x)) /* 0xb0 - 0xb7 */
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#define ADV7511_REG_HDCP_STATUS 0xb8
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#define ADV7511_REG_BCAPS 0xbe
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#define ADV7511_REG_BKSV(x) (0xc0 + (x)) /* 0xc0 - 0xc3 */
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#define ADV7511_REG_EDID_SEGMENT 0xc4
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#define ADV7511_REG_DDC_STATUS 0xc8
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#define ADV7511_REG_EDID_READ_CTRL 0xc9
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#define ADV7511_REG_BSTATUS(x) (0xca + (x)) /* 0xca - 0xcb */
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#define ADV7511_REG_TIMING_GEN_SEQ 0xd0
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#define ADV7511_REG_POWER2 0xd6
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#define ADV7511_REG_HSYNC_PLACEMENT_MSB 0xfa
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#define ADV7511_REG_SYNC_ADJUSTMENT(x) (0xd7 + (x)) /* 0xd7 - 0xdc */
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#define ADV7511_REG_TMDS_CLOCK_INV 0xde
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#define ADV7511_REG_ARC_CTRL 0xdf
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#define ADV7511_REG_CEC_I2C_ADDR 0xe1
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#define ADV7511_REG_CEC_CTRL 0xe2
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#define ADV7511_REG_CHIP_ID_HIGH 0xf5
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#define ADV7511_REG_CHIP_ID_LOW 0xf6
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/* Hardware defined default addresses for I2C register maps */
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#define ADV7511_CEC_I2C_ADDR_DEFAULT 0x3c
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#define ADV7511_EDID_I2C_ADDR_DEFAULT 0x3f
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#define ADV7511_PACKET_I2C_ADDR_DEFAULT 0x38
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#define ADV7511_CSC_ENABLE BIT(7)
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#define ADV7511_CSC_UPDATE_MODE BIT(5)
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#define ADV7511_INT0_HPD BIT(7)
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#define ADV7511_INT0_VSYNC BIT(5)
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#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
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#define ADV7511_INT0_EDID_READY BIT(2)
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#define ADV7511_INT0_HDCP_AUTHENTICATED BIT(1)
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#define ADV7511_INT1_DDC_ERROR BIT(7)
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#define ADV7511_INT1_BKSV BIT(6)
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#define ADV7511_INT1_CEC_TX_READY BIT(5)
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#define ADV7511_INT1_CEC_TX_ARBIT_LOST BIT(4)
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#define ADV7511_INT1_CEC_TX_RETRY_TIMEOUT BIT(3)
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#define ADV7511_INT1_CEC_RX_READY3 BIT(2)
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#define ADV7511_INT1_CEC_RX_READY2 BIT(1)
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#define ADV7511_INT1_CEC_RX_READY1 BIT(0)
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#define ADV7511_ARC_CTRL_POWER_DOWN BIT(0)
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#define ADV7511_CEC_CTRL_POWER_DOWN BIT(0)
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#define ADV7511_POWER_POWER_DOWN BIT(6)
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#define ADV7511_HDMI_CFG_MODE_MASK 0x2
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#define ADV7511_HDMI_CFG_MODE_DVI 0x0
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#define ADV7511_HDMI_CFG_MODE_HDMI 0x2
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#define ADV7511_AUDIO_SELECT_I2C 0x0
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#define ADV7511_AUDIO_SELECT_SPDIF 0x1
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#define ADV7511_AUDIO_SELECT_DSD 0x2
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#define ADV7511_AUDIO_SELECT_HBR 0x3
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#define ADV7511_AUDIO_SELECT_DST 0x4
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#define ADV7511_I2S_SAMPLE_LEN_16 0x2
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#define ADV7511_I2S_SAMPLE_LEN_20 0x3
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#define ADV7511_I2S_SAMPLE_LEN_18 0x4
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#define ADV7511_I2S_SAMPLE_LEN_22 0x5
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#define ADV7511_I2S_SAMPLE_LEN_19 0x8
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#define ADV7511_I2S_SAMPLE_LEN_23 0x9
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#define ADV7511_I2S_SAMPLE_LEN_24 0xb
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#define ADV7511_I2S_SAMPLE_LEN_17 0xc
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#define ADV7511_I2S_SAMPLE_LEN_21 0xd
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#define ADV7511_SAMPLE_FREQ_44100 0x0
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#define ADV7511_SAMPLE_FREQ_48000 0x2
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#define ADV7511_SAMPLE_FREQ_32000 0x3
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#define ADV7511_SAMPLE_FREQ_88200 0x8
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#define ADV7511_SAMPLE_FREQ_96000 0xa
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#define ADV7511_SAMPLE_FREQ_176400 0xc
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#define ADV7511_SAMPLE_FREQ_192000 0xe
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#define ADV7511_STATUS_POWER_DOWN_POLARITY BIT(7)
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#define ADV7511_STATUS_HPD BIT(6)
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#define ADV7511_STATUS_MONITOR_SENSE BIT(5)
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#define ADV7511_STATUS_I2S_32BIT_MODE BIT(3)
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#define ADV7511_PACKET_ENABLE_N_CTS BIT(8+6)
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#define ADV7511_PACKET_ENABLE_AUDIO_SAMPLE BIT(8+5)
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#define ADV7511_PACKET_ENABLE_AVI_INFOFRAME BIT(8+4)
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#define ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME BIT(8+3)
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#define ADV7511_PACKET_ENABLE_GC BIT(7)
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#define ADV7511_PACKET_ENABLE_SPD BIT(6)
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#define ADV7511_PACKET_ENABLE_MPEG BIT(5)
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#define ADV7511_PACKET_ENABLE_ACP BIT(4)
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#define ADV7511_PACKET_ENABLE_ISRC BIT(3)
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#define ADV7511_PACKET_ENABLE_GM BIT(2)
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#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
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#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
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#define ADV7535_REG_POWER2_HPD_OVERRIDE BIT(6)
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#define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
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#define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
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#define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
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#define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
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#define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
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#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
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#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
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#define ADV7511_LOW_REFRESH_RATE_NONE 0x0
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#define ADV7511_LOW_REFRESH_RATE_24HZ 0x1
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#define ADV7511_LOW_REFRESH_RATE_25HZ 0x2
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#define ADV7511_LOW_REFRESH_RATE_30HZ 0x3
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#define ADV7511_AUDIO_CFG3_LEN_MASK 0x0f
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#define ADV7511_I2C_FREQ_ID_CFG_RATE_MASK 0xf0
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#define ADV7511_AUDIO_SOURCE_I2S 0
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#define ADV7511_AUDIO_SOURCE_SPDIF 1
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#define ADV7511_I2S_FORMAT_I2S 0
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#define ADV7511_I2S_FORMAT_RIGHT_J 1
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#define ADV7511_I2S_FORMAT_LEFT_J 2
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#define ADV7511_I2S_IEC958_DIRECT 3
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#define ADV7511_PACKET(p, x) ((p) * 0x20 + (x))
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#define ADV7511_PACKET_SDP(x) ADV7511_PACKET(0, x)
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#define ADV7511_PACKET_MPEG(x) ADV7511_PACKET(1, x)
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#define ADV7511_PACKET_ACP(x) ADV7511_PACKET(2, x)
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#define ADV7511_PACKET_ISRC1(x) ADV7511_PACKET(3, x)
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#define ADV7511_PACKET_ISRC2(x) ADV7511_PACKET(4, x)
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#define ADV7511_PACKET_GM(x) ADV7511_PACKET(5, x)
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#define ADV7511_PACKET_SPARE(x) ADV7511_PACKET(6, x)
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#define ADV7511_REG_CEC_TX_FRAME_HDR 0x00
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#define ADV7511_REG_CEC_TX_FRAME_DATA0 0x01
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#define ADV7511_REG_CEC_TX_FRAME_LEN 0x10
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#define ADV7511_REG_CEC_TX_ENABLE 0x11
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#define ADV7511_REG_CEC_TX_RETRY 0x12
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#define ADV7511_REG_CEC_TX_LOW_DRV_CNT 0x14
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#define ADV7511_REG_CEC_RX_FRAME_HDR 0x15
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#define ADV7511_REG_CEC_RX_FRAME_DATA0 0x16
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#define ADV7511_REG_CEC_RX_FRAME_LEN 0x25
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#define ADV7511_REG_CEC_RX_ENABLE 0x26
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#define ADV7511_REG_CEC_RX_BUFFERS 0x4a
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#define ADV7511_REG_CEC_LOG_ADDR_MASK 0x4b
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#define ADV7511_REG_CEC_LOG_ADDR_0_1 0x4c
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#define ADV7511_REG_CEC_LOG_ADDR_2 0x4d
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#define ADV7511_REG_CEC_CLK_DIV 0x4e
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#define ADV7511_REG_CEC_SOFT_RESET 0x50
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#define ADV7533_REG_CEC_OFFSET 0x70
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enum adv7511_input_clock {
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ADV7511_INPUT_CLOCK_1X,
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ADV7511_INPUT_CLOCK_2X,
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ADV7511_INPUT_CLOCK_DDR,
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};
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enum adv7511_input_justification {
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ADV7511_INPUT_JUSTIFICATION_EVENLY = 0,
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ADV7511_INPUT_JUSTIFICATION_RIGHT = 1,
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ADV7511_INPUT_JUSTIFICATION_LEFT = 2,
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};
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enum adv7511_input_sync_pulse {
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ADV7511_INPUT_SYNC_PULSE_DE = 0,
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ADV7511_INPUT_SYNC_PULSE_HSYNC = 1,
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ADV7511_INPUT_SYNC_PULSE_VSYNC = 2,
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ADV7511_INPUT_SYNC_PULSE_NONE = 3,
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};
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/**
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* enum adv7511_sync_polarity - Polarity for the input sync signals
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* @ADV7511_SYNC_POLARITY_PASSTHROUGH: Sync polarity matches that of
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* the currently configured mode.
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* @ADV7511_SYNC_POLARITY_LOW: Sync polarity is low
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* @ADV7511_SYNC_POLARITY_HIGH: Sync polarity is high
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*
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* If the polarity is set to either LOW or HIGH the driver will configure the
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* ADV7511 to internally invert the sync signal if required to match the sync
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* polarity setting for the currently selected output mode.
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*
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* If the polarity is set to PASSTHROUGH, the ADV7511 will route the signal
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* unchanged. This is used when the upstream graphics core already generates
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* the sync signals with the correct polarity.
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*/
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enum adv7511_sync_polarity {
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ADV7511_SYNC_POLARITY_PASSTHROUGH,
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ADV7511_SYNC_POLARITY_LOW,
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ADV7511_SYNC_POLARITY_HIGH,
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};
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/**
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* struct adv7511_link_config - Describes adv7511 hardware configuration
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* @input_color_depth: Number of bits per color component (8, 10 or 12)
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* @input_colorspace: The input colorspace (RGB, YUV444, YUV422)
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* @input_clock: The input video clock style (1x, 2x, DDR)
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* @input_style: The input component arrangement variant
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* @input_justification: Video input format bit justification
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* @clock_delay: Clock delay for the input clock (in ps)
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* @embedded_sync: Video input uses BT.656-style embedded sync
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* @sync_pulse: Select the sync pulse
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* @vsync_polarity: vsync input signal configuration
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* @hsync_polarity: hsync input signal configuration
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*/
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struct adv7511_link_config {
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unsigned int input_color_depth;
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enum hdmi_colorspace input_colorspace;
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enum adv7511_input_clock input_clock;
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unsigned int input_style;
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enum adv7511_input_justification input_justification;
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int clock_delay;
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bool embedded_sync;
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enum adv7511_input_sync_pulse sync_pulse;
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enum adv7511_sync_polarity vsync_polarity;
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enum adv7511_sync_polarity hsync_polarity;
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};
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/**
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* enum adv7511_csc_scaling - Scaling factor for the ADV7511 CSC
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* @ADV7511_CSC_SCALING_1: CSC results are not scaled
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* @ADV7511_CSC_SCALING_2: CSC results are scaled by a factor of two
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* @ADV7511_CSC_SCALING_4: CSC results are scalled by a factor of four
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*/
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enum adv7511_csc_scaling {
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ADV7511_CSC_SCALING_1 = 0,
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ADV7511_CSC_SCALING_2 = 1,
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ADV7511_CSC_SCALING_4 = 2,
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};
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/**
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* struct adv7511_video_config - Describes adv7511 hardware configuration
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* @csc_enable: Whether to enable color space conversion
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* @csc_scaling_factor: Color space conversion scaling factor
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* @csc_coefficents: Color space conversion coefficents
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* @hdmi_mode: Whether to use HDMI or DVI output mode
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* @avi_infoframe: HDMI infoframe
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*/
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struct adv7511_video_config {
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bool csc_enable;
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enum adv7511_csc_scaling csc_scaling_factor;
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const uint16_t *csc_coefficents;
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bool hdmi_mode;
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struct hdmi_avi_infoframe avi_infoframe;
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};
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enum adv7511_type {
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ADV7511,
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ADV7533,
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ADV7535,
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};
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#define ADV7511_MAX_ADDRS 3
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struct adv7511 {
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struct i2c_client *i2c_main;
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struct i2c_client *i2c_edid;
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struct i2c_client *i2c_packet;
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struct i2c_client *i2c_cec;
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struct regmap *regmap;
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struct regmap *regmap_cec;
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enum drm_connector_status status;
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bool powered;
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struct drm_display_mode curr_mode;
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unsigned int f_tmds;
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unsigned int f_audio;
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unsigned int audio_source;
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unsigned int current_edid_segment;
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uint8_t edid_buf[256];
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bool edid_read;
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wait_queue_head_t wq;
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struct work_struct hpd_work;
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struct drm_bridge bridge;
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struct drm_connector connector;
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bool embedded_sync;
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enum adv7511_sync_polarity vsync_polarity;
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enum adv7511_sync_polarity hsync_polarity;
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bool rgb;
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struct gpio_desc *gpio_pd;
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struct regulator_bulk_data *supplies;
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unsigned int num_supplies;
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/* ADV7533 DSI RX related params */
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struct device_node *host_node;
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struct mipi_dsi_device *dsi;
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u8 num_dsi_lanes;
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bool use_timing_gen;
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enum adv7511_type type;
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struct platform_device *audio_pdev;
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struct cec_adapter *cec_adap;
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u8 cec_addr[ADV7511_MAX_ADDRS];
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u8 cec_valid_addrs;
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bool cec_enabled_adap;
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struct clk *cec_clk;
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u32 cec_clk_freq;
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};
|
|
|
|
#ifdef CONFIG_DRM_I2C_ADV7511_CEC
|
|
int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511);
|
|
void adv7511_cec_irq_process(struct adv7511 *adv7511, unsigned int irq1);
|
|
#else
|
|
static inline int adv7511_cec_init(struct device *dev, struct adv7511 *adv7511)
|
|
{
|
|
regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
|
|
ADV7511_CEC_CTRL_POWER_DOWN);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
void adv7533_dsi_power_on(struct adv7511 *adv);
|
|
void adv7533_dsi_power_off(struct adv7511 *adv);
|
|
enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
|
|
const struct drm_display_mode *mode);
|
|
int adv7533_patch_registers(struct adv7511 *adv);
|
|
int adv7533_patch_cec_registers(struct adv7511 *adv);
|
|
int adv7533_attach_dsi(struct adv7511 *adv);
|
|
void adv7533_detach_dsi(struct adv7511 *adv);
|
|
int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv);
|
|
|
|
#ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
|
|
int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511);
|
|
void adv7511_audio_exit(struct adv7511 *adv7511);
|
|
#else /*CONFIG_DRM_I2C_ADV7511_AUDIO */
|
|
static inline int adv7511_audio_init(struct device *dev, struct adv7511 *adv7511)
|
|
{
|
|
return 0;
|
|
}
|
|
static inline void adv7511_audio_exit(struct adv7511 *adv7511)
|
|
{
|
|
}
|
|
#endif /* CONFIG_DRM_I2C_ADV7511_AUDIO */
|
|
|
|
#endif /* __DRM_I2C_ADV7511_H__ */
|