142 lines
4.2 KiB
C
142 lines
4.2 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2020 Intel Corporation */
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#include "adf_accel_devices.h"
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#include "adf_gen4_hw_data.h"
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static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
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{
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return BUILD_RING_BASE_ADDR(addr, size);
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}
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static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
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}
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static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
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}
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static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
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{
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return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
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}
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static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
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}
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static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
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{
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return READ_CSR_E_STAT(csr_base_addr, bank);
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}
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static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
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u32 value)
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{
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WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
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}
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static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
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dma_addr_t addr)
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{
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WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
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}
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static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
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}
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static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
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{
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WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
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}
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static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
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{
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WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
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}
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static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
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}
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static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
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}
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static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
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u32 value)
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{
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WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
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}
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void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
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{
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csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
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csr_ops->read_csr_ring_head = read_csr_ring_head;
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csr_ops->write_csr_ring_head = write_csr_ring_head;
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csr_ops->read_csr_ring_tail = read_csr_ring_tail;
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csr_ops->write_csr_ring_tail = write_csr_ring_tail;
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csr_ops->read_csr_e_stat = read_csr_e_stat;
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csr_ops->write_csr_ring_config = write_csr_ring_config;
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csr_ops->write_csr_ring_base = write_csr_ring_base;
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csr_ops->write_csr_int_flag = write_csr_int_flag;
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csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
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csr_ops->write_csr_int_col_en = write_csr_int_col_en;
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csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
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csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
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csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
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}
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EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);
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static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper,
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u32 *lower)
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{
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*lower = lower_32_bits(value);
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*upper = upper_32_bits(value);
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}
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void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev)
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{
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struct adf_hw_device_data *hw_data = accel_dev->hw_device;
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u64 timer_val_pke = ADF_SSM_WDT_PKE_DEFAULT_VALUE;
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u64 timer_val = ADF_SSM_WDT_DEFAULT_VALUE;
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u32 ssm_wdt_pke_high = 0;
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u32 ssm_wdt_pke_low = 0;
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u32 ssm_wdt_high = 0;
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u32 ssm_wdt_low = 0;
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void __iomem *pmisc_addr;
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struct adf_bar *pmisc;
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int pmisc_id;
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pmisc_id = hw_data->get_misc_bar_id(hw_data);
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pmisc = &GET_BARS(accel_dev)[pmisc_id];
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pmisc_addr = pmisc->virt_addr;
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/* Convert 64bit WDT timer value into 32bit values for
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* mmio write to 32bit CSRs.
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*/
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adf_gen4_unpack_ssm_wdtimer(timer_val, &ssm_wdt_high, &ssm_wdt_low);
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adf_gen4_unpack_ssm_wdtimer(timer_val_pke, &ssm_wdt_pke_high,
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&ssm_wdt_pke_low);
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/* Enable WDT for sym and dc */
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDTL_OFFSET, ssm_wdt_low);
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDTH_OFFSET, ssm_wdt_high);
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/* Enable WDT for pke */
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEL_OFFSET, ssm_wdt_pke_low);
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ADF_CSR_WR(pmisc_addr, ADF_SSMWDTPKEH_OFFSET, ssm_wdt_pke_high);
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}
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EXPORT_SYMBOL_GPL(adf_gen4_set_ssm_wdtimer);
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