219 lines
6.3 KiB
Plaintext
219 lines
6.3 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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comment "Processor Features"
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config CPU_BIG_ENDIAN
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def_bool !CPU_LITTLE_ENDIAN
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config CPU_LITTLE_ENDIAN
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bool "Little endian"
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default y
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config FPU
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bool "FPU support"
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default n
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help
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If FPU ISA is used in user space, this configuration shall be Y to
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enable required support in kernel such as fpu context switch and
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fpu exception handler.
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If no FPU ISA is used in user space, say N.
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config LAZY_FPU
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bool "lazy FPU support"
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depends on FPU
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default y
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help
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Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
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enhance system performance by reducing the context switch
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frequency of the FPU register.
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For normal case, say Y.
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config SUPPORT_DENORMAL_ARITHMETIC
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bool "Denormal arithmetic support"
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depends on FPU
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default n
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help
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Say Y here to enable arithmetic of denormalized number. Enabling
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this feature can enhance the precision for tininess number.
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However, performance loss in float point calculations is
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possibly significant due to additional FPU exception.
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If the calculated tolerance for tininess number is not critical,
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say N to prevent performance loss.
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config HWZOL
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bool "hardware zero overhead loop support"
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depends on CPU_D10 || CPU_D15
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default n
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help
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A set of Zero-Overhead Loop mechanism is provided to reduce the
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instruction fetch and execution overhead of loop-control instructions.
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It will save 3 registers($LB, $LC, $LE) for context saving if say Y.
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You don't need to save these registers if you can make sure your user
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program doesn't use these registers.
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If unsure, say N.
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config CPU_CACHE_ALIASING
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bool "Aliasing cache"
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depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3
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default y
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help
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If this CPU is using VIPT data cache and its cache way size is larger
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than page size, say Y. If it is using PIPT data cache, say N.
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If unsure, say Y.
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choice
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prompt "minimum CPU type"
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default CPU_V3
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help
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The data cache of N15/D15 is implemented as PIPT and it will not cause
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the cache aliasing issue. The rest cpus(N13, N10 and D10) are
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implemented as VIPT data cache. It may cause the cache aliasing issue
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if its cache way size is larger than page size. You can specify the
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CPU type directly or choose CPU_V3 if unsure.
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A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
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A kernel built for N15 is able to run on N15 or D15.
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A kernel built for D10 is able to run on D10 or D15.
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A kernel built for D15 is able to run on D15.
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A kernel built for N13 is able to run on N15, N13 or D15.
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config CPU_N15
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bool "AndesCore N15"
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config CPU_N13
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bool "AndesCore N13"
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select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB
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config CPU_N10
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bool "AndesCore N10"
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select CPU_CACHE_ALIASING
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config CPU_D15
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bool "AndesCore D15"
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config CPU_D10
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bool "AndesCore D10"
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select CPU_CACHE_ALIASING
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config CPU_V3
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bool "AndesCore v3 compatible"
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select CPU_CACHE_ALIASING
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endchoice
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choice
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prompt "Paging -- page size "
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default ANDES_PAGE_SIZE_4KB
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config ANDES_PAGE_SIZE_4KB
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bool "use 4KB page size"
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config ANDES_PAGE_SIZE_8KB
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bool "use 8KB page size"
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endchoice
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config CPU_ICACHE_DISABLE
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bool "Disable I-Cache"
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help
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Say Y here to disable the processor instruction cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_DISABLE
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bool "Disable D-Cache"
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help
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on !CPU_DCACHE_DISABLE
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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specifically require this or are unsure, say N.
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config WBNA
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bool "WBNA"
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default n
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help
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Say Y here to enable write-back memory with no-write-allocation policy.
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config ALIGNMENT_TRAP
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bool "Kernel support unaligned access handling by sw"
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depends on PROC_FS
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default n
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help
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Andes processors cannot load/store information which is not
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naturally aligned on the bus, i.e., a 4 byte load must start at an
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address divisible by 4. On 32-bit Andes processors, these non-aligned
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load/store instructions will be emulated in software if you say Y
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here, which has a severe performance impact. With an IP-only
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configuration it is safe to say N, otherwise say Y.
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config HW_SUPPORT_UNALIGNMENT_ACCESS
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bool "Kernel support unaligned access handling by hw"
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depends on !ALIGNMENT_TRAP
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default n
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help
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Andes processors load/store world/half-word instructions can access
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unaligned memory locations without generating the Data Alignment
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Check exceptions. With an IP-only configuration it is safe to say N,
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otherwise say Y.
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config HIGHMEM
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bool "High Memory Support"
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depends on MMU && !CPU_CACHE_ALIASING
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select KMAP_LOCAL
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help
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The address space of Andes processors is only 4 Gigabytes large
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and it has to accommodate user address space, kernel address
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space as well as some memory mapped IO. That means that, if you
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have a large amount of physical memory and/or IO, not all of the
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memory can be "permanently mapped" by the kernel. The physical
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memory that is not permanently mapped is called "high memory".
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Depending on the selected kernel/user memory split, minimum
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vmalloc space and actual amount of RAM, you may not need this
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option which should result in a slightly faster kernel.
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If unsure, say N.
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config CACHE_L2
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bool "Support L2 cache"
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default y
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help
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Say Y here to enable L2 cache if your SoC are integrated with L2CC.
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If unsure, say N.
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config HW_PRE
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bool "Enable hardware prefetcher"
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default y
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help
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Say Y here to enable hardware prefetcher feature.
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Only when CPU_VER.REV >= 0x09 can support.
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menu "Memory configuration"
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choice
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prompt "Memory split"
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depends on MMU
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default VMSPLIT_3G_OPT
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help
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Select the desired split between kernel and user memory.
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If you are not absolutely sure what you are doing, leave this
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option alone!
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config VMSPLIT_3G
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bool "3G/1G user/kernel split"
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config VMSPLIT_3G_OPT
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bool "3G/1G user/kernel split (for full 1G low memory)"
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config VMSPLIT_2G
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bool "2G/2G user/kernel split"
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config VMSPLIT_1G
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bool "1G/3G user/kernel split"
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endchoice
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config PAGE_OFFSET
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hex
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default 0x40000000 if VMSPLIT_1G
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default 0x80000000 if VMSPLIT_2G
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default 0xB0000000 if VMSPLIT_3G_OPT
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default 0xC0000000
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endmenu
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