kernel/Documentation/devicetree/bindings/thermal/thermal-idle.yaml
2024-07-22 17:22:30 +08:00

147 lines
4.9 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2020 Linaro Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/thermal-idle.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Thermal idle cooling device binding
maintainers:
- Daniel Lezcano <daniel.lezcano@linaro.org>
description: |
The thermal idle cooling device allows the system to passively
mitigate the temperature on the device by injecting idle cycles,
forcing it to cool down.
This binding describes the thermal idle node.
properties:
$nodename:
const: thermal-idle
description: |
A thermal-idle node describes the idle cooling device properties to
cool down efficiently the attached thermal zone.
'#cooling-cells':
const: 2
description: |
Must be 2, in order to specify minimum and maximum cooling state used in
the cooling-maps reference. The first cell is the minimum cooling state
and the second cell is the maximum cooling state requested.
duration-us:
description: |
The idle duration in microsecond the device should cool down.
exit-latency-us:
description: |
The exit latency constraint in microsecond for the injected idle state
for the device. It is the latency constraint to apply when selecting an
idle state from among all the present ones.
required:
- '#cooling-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/thermal/thermal.h>
// Example: Combining idle cooling device on big CPUs with cpufreq cooling device
cpus {
#address-cells = <2>;
#size-cells = <0>;
/* ... */
cpu_b0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <436>;
#cooling-cells = <2>; /* min followed by max */
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
cpu_b1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <436>;
#cooling-cells = <2>; /* min followed by max */
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
thermal-idle {
#cooling-cells = <2>;
duration-us = <10000>;
exit-latency-us = <500>;
};
};
/* ... */
};
/* ... */
thermal_zones {
cpu_thermal: cpu {
polling-delay-passive = <100>;
polling-delay = <1000>;
/* ... */
trips {
cpu_alert0: cpu_alert0 {
temperature = <65000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
cpu_alert2: cpu_alert2 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >,
<&{/cpus/cpu@101/thermal-idle} 0 15>;
};
map1 {
trip = <&cpu_alert2>;
cooling-device =
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};