45 lines
1.5 KiB
Plaintext
45 lines
1.5 KiB
Plaintext
MediaTek display PWM controller
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Required properties:
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- compatible: should be "mediatek,<name>-disp-pwm":
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- "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
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- "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
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- "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
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- "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
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- reg: physical base address and length of the controller's registers.
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- #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
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the cell format.
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- clocks: phandle and clock specifier of the PWM reference clock.
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- clock-names: must contain the following:
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- "main": clock used to generate PWM signals.
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- "mm": sync signals from the modules of mmsys.
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-0: One property must exist for each entry in pinctrl-names.
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See pinctrl/pinctrl-bindings.txt for details of the property values.
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Example:
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm",
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"mediatek,mt6595-disp-pwm";
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reg = <0 0x1401e000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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<&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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pinctrl-names = "default";
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pinctrl-0 = <&disp_pwm0_pins>;
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};
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backlight_lcd: backlight_lcd {
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compatible = "pwm-backlight";
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pwms = <&pwm0 0 1000000>;
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brightness-levels = <
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0 16 32 48 64 80 96 112
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128 144 160 176 192 208 224 240
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255
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>;
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default-brightness-level = <9>;
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power-supply = <&mt6397_vio18_reg>;
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enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
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};
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