240 lines
9.0 KiB
YAML
240 lines
9.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Actions Semi S500 SoC pinmux & GPIO controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
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description: |
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Pinmux & GPIO controller manages pin multiplexing & configuration including
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GPIO function selection & GPIO attributes configuration. Please refer to
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pinctrl-bindings.txt in this directory for common binding part and usage.
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properties:
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compatible:
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const: actions,s500-pinctrl
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reg:
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items:
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- description: GPIO Output + GPIO Input + GPIO Data
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- description: Multiplexing Control
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- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
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- description: PAD Drive Capacity Select
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minItems: 1
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clocks:
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maxItems: 1
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gpio-controller: true
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gpio-ranges:
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maxItems: 1
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'#gpio-cells':
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description:
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Specifies the pin number and flags, as defined in
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include/dt-bindings/gpio/gpio.h
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const: 2
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interrupt-controller: true
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'#interrupt-cells':
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description:
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Specifies the pin number and flags, as defined in
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include/dt-bindings/interrupt-controller/irq.h
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const: 2
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interrupts:
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description:
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One interrupt per each of the 5 GPIO ports supported by the controller,
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sorted by port number ascending order.
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minItems: 5
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maxItems: 5
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patternProperties:
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'-pins$':
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type: object
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patternProperties:
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'^(.*-)?pinmux$':
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type: object
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description:
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Pinctrl node's client devices specify pin muxes using subnodes,
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which in turn use the standard properties below.
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$ref: pinmux-node.yaml#
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properties:
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groups:
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description:
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List of gpio pin groups affected by the functions specified in
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this subnode.
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items:
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oneOf:
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- enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
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rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
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rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
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i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
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ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
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ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
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dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
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dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
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spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
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dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
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uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
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sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
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uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
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uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
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pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
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dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
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nand_ceb3_mfp]
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minItems: 1
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maxItems: 32
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function:
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description:
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Specify the alternative function to be configured for the
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given gpio pin groups.
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enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
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sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
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i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
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p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
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mipi_csi, nand, spdif, ts, lcd0]
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required:
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- groups
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- function
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additionalProperties: false
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'^(.*-)?pinconf$':
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type: object
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description:
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Pinctrl node's client devices specify pin configurations using
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subnodes, which in turn use the standard properties below.
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$ref: pincfg-node.yaml#
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properties:
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groups:
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description:
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List of gpio pin groups affected by the drive-strength property
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specified in this subnode.
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items:
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oneOf:
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- enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
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rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
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smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
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i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
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lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
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sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
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spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
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i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
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sens0_ckout_drv, uart3_all_drv]
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minItems: 1
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maxItems: 32
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pins:
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description:
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List of gpio pins affected by the bias-pull-* and
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input-schmitt-* properties specified in this subnode.
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items:
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oneOf:
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- enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
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eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
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eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
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i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
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i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
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ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
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lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
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lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
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lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
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dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
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dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
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sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
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spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
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uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
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sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
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dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
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uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
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pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
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i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
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csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
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csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
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dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
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dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
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pkg2, pkg3]
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minItems: 1
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maxItems: 64
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bias-pull-up: true
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bias-pull-down: true
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drive-strength:
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description:
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Selects the drive strength for the specified pins, in mA.
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enum: [2, 4, 8, 12]
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input-schmitt-enable: true
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input-schmitt-disable: true
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- gpio-controller
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- gpio-ranges
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- '#gpio-cells'
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl: pinctrl@b01b0000 {
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compatible = "actions,s500-pinctrl";
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reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
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<0xb01b0060 0x18>, <0xb01b0080 0xc>;
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clocks = <&cmu 55>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 132>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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mmc0_pins: mmc0-pins {
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pinmux {
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groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
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"sd0_cmd_mfp", "sd0_clk_mfp";
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function = "sd0";
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};
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drv-pinconf {
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groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
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drive-strength = <8>;
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};
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bias-pinconf {
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pins = "sd0_d0", "sd0_d1", "sd0_d2",
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"sd0_d3", "sd0_cmd";
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bias-pull-up;
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};
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};
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};
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...
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