114 lines
3.1 KiB
YAML
114 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive FU740 PCIe host controller
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description: |+
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SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
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PCI core. It shares common features with the PCIe DesignWare core and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Greentime Hu <greentime.hu@sifive.com>
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: sifive,fu740-pcie
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: mgmt
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num-lanes:
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const: 8
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msi-parent: true
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interrupt-names:
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items:
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- const: msi
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- const: inta
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- const: intb
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- const: intc
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- const: intd
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resets:
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description: A phandle to the PCIe power up reset line.
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maxItems: 1
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pwren-gpios:
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description: Should specify the GPIO for controlling the PCI bus device power on.
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maxItems: 1
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reset-gpios:
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maxItems: 1
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required:
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- dma-coherent
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- num-lanes
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- interrupts
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- interrupt-names
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- interrupt-parent
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- interrupt-map-mask
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- interrupt-map
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- clock-names
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- clocks
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- resets
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- pwren-gpios
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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pcie@e00000000 {
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compatible = "sifive,fu740-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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reg = <0xe 0x00000000 0x0 0x80000000>,
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<0xd 0xf0000000 0x0 0x10000000>,
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<0x0 0x100d0000 0x0 0x1000>;
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reg-names = "dbi", "config", "mgmt";
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device_type = "pci";
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dma-coherent;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
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<0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
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<0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
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num-lanes = <0x8>;
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interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-parent = <&plic0>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
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<0x0 0x0 0x0 0x2 &plic0 58>,
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<0x0 0x0 0x0 0x3 &plic0 59>,
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<0x0 0x0 0x0 0x4 &plic0 60>;
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clock-names = "pcie_aux";
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clocks = <&prci PRCI_CLK_PCIE_AUX>;
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resets = <&prci 4>;
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pwren-gpios = <&gpio 5 0>;
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reset-gpios = <&gpio 8 0>;
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};
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};
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