68 lines
1.9 KiB
Plaintext
68 lines
1.9 KiB
Plaintext
* Faraday Technology FTGMAC100 gigabit ethernet controller
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Required properties:
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- compatible: "faraday,ftgmac100"
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Must also contain one of these if used as part of an Aspeed AST2400
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or 2500 family SoC as they have some subtle tweaks to the
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implementation:
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- "aspeed,ast2400-mac"
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- "aspeed,ast2500-mac"
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- "aspeed,ast2600-mac"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain ethernet controller interrupt
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Optional properties:
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- phy-handle: See ethernet.txt file in the same directory.
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- phy-mode: See ethernet.txt file in the same directory. If the property is
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absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for
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aspeed parts. Other (unknown) parts will accept any value.
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- use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes
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rmii (100bT) but kept as a separate property in case NC-SI grows support
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for a gigabit link.
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- no-hw-checksum: Used to disable HW checksum support. Here for backward
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compatibility as the driver now should have correct defaults based on
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the SoC.
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- clocks: In accordance with the generic clock bindings. Must describe the MAC
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IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
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required MAC clock must be the first cell.
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- clock-names:
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- "MACCLK": The MAC IP clock
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- "RCLK": Clock gate for the RMII RCLK
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Optional subnodes:
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- mdio: See mdio.txt file in the same directory.
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Example:
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mac0: ethernet@1e660000 {
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compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
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reg = <0x1e660000 0x180>;
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interrupts = <2>;
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use-ncsi;
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};
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Example with phy-handle:
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mac1: ethernet@1e680000 {
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compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
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reg = <0x1e680000 0x180>;
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interrupts = <2>;
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phy-handle = <&phy>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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