158 lines
4.8 KiB
Plaintext
158 lines
4.8 KiB
Plaintext
======================================================================
|
|
Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
|
|
======================================================================
|
|
|
|
The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
|
|
peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
|
|
primary use case of the Aspeed LPC controller is as a slave on the bus
|
|
(typically in a Baseboard Management Controller SoC), but under certain
|
|
conditions it can also take the role of bus master.
|
|
|
|
The LPC controller is represented as a multi-function device to account for the
|
|
mix of functionality, which includes, but is not limited to:
|
|
|
|
* An IPMI Block Transfer[2] Controller
|
|
|
|
* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
|
|
physical properties of some LPC pins, configuration of serial IRQs, and
|
|
APB-to-LPC bridging amonst other functions.
|
|
|
|
* An LPC Host Interface Controller: Manages functions exposed to the host such
|
|
as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
|
|
management and bus snoop configuration.
|
|
|
|
* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
|
|
hardware management protocols for handover between the host and baseboard
|
|
management controller.
|
|
|
|
Additionally the state of the LPC controller influences the pinmux
|
|
configuration, therefore the host portion of the controller is exposed as a
|
|
syscon as a means to arbitrate access.
|
|
|
|
[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
|
|
[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
|
|
[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
|
|
[3] https://en.wikipedia.org/wiki/Super_I/O
|
|
|
|
Required properties
|
|
===================
|
|
|
|
- compatible: One of:
|
|
"aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
|
|
"aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
|
|
"aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
|
|
|
|
- reg: contains the physical address and length values of the Aspeed
|
|
LPC memory region.
|
|
|
|
- #address-cells: <1>
|
|
- #size-cells: <1>
|
|
- ranges: Maps 0 to the physical address and length of the LPC memory
|
|
region
|
|
|
|
Example:
|
|
|
|
lpc: lpc@1e789000 {
|
|
compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
|
|
reg = <0x1e789000 0x1000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1e789000 0x1000>;
|
|
|
|
lpc_snoop: lpc-snoop@0 {
|
|
compatible = "aspeed,ast2600-lpc-snoop";
|
|
reg = <0x0 0x80>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
snoop-ports = <0x80>;
|
|
};
|
|
};
|
|
|
|
|
|
LPC Host Interface Controller
|
|
-------------------
|
|
|
|
The LPC Host Interface Controller manages functions exposed to the host such as
|
|
LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
|
|
management and bus snoop configuration.
|
|
|
|
Required properties:
|
|
|
|
- compatible: One of:
|
|
"aspeed,ast2400-lpc-ctrl";
|
|
"aspeed,ast2500-lpc-ctrl";
|
|
"aspeed,ast2600-lpc-ctrl";
|
|
|
|
- reg: contains offset/length values of the host interface controller
|
|
memory regions
|
|
|
|
- clocks: contains a phandle to the syscon node describing the clocks.
|
|
There should then be one cell representing the clock to use
|
|
|
|
Optional properties:
|
|
|
|
- memory-region: A phandle to a reserved_memory region to be used for the LPC
|
|
to AHB mapping
|
|
|
|
- flash: A phandle to the SPI flash controller containing the flash to
|
|
be exposed over the LPC to AHB mapping
|
|
|
|
Example:
|
|
|
|
lpc_ctrl: lpc-ctrl@80 {
|
|
compatible = "aspeed,ast2500-lpc-ctrl";
|
|
reg = <0x80 0x80>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
|
|
memory-region = <&flash_memory>;
|
|
flash = <&spi>;
|
|
};
|
|
|
|
LPC Host Controller
|
|
-------------------
|
|
|
|
The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
|
|
between the host and the baseboard management controller. The registers exist
|
|
in the "host" portion of the Aspeed LPC controller, which must be the parent of
|
|
the LPC host controller node.
|
|
|
|
Required properties:
|
|
|
|
- compatible: One of:
|
|
"aspeed,ast2400-lhc";
|
|
"aspeed,ast2500-lhc";
|
|
"aspeed,ast2600-lhc";
|
|
|
|
- reg: contains offset/length values of the LHC memory regions. In the
|
|
AST2400 and AST2500 there are two regions.
|
|
|
|
Example:
|
|
|
|
lhc: lhc@a0 {
|
|
compatible = "aspeed,ast2500-lhc";
|
|
reg = <0xa0 0x24 0xc8 0x8>;
|
|
};
|
|
|
|
LPC reset control
|
|
-----------------
|
|
|
|
The UARTs present in the ASPEED SoC can have their resets tied to the reset
|
|
state of the LPC bus. Some systems may chose to modify this configuration.
|
|
|
|
Required properties:
|
|
|
|
- compatible: One of:
|
|
"aspeed,ast2600-lpc-reset";
|
|
"aspeed,ast2500-lpc-reset";
|
|
"aspeed,ast2400-lpc-reset";
|
|
|
|
- reg: offset and length of the IP in the LHC memory region
|
|
- #reset-controller indicates the number of reset cells expected
|
|
|
|
Example:
|
|
|
|
lpc_reset: reset-controller@98 {
|
|
compatible = "aspeed,ast2500-lpc-reset";
|
|
reg = <0x98 0x4>;
|
|
#reset-cells = <1>;
|
|
};
|