37 lines
1.5 KiB
Plaintext
37 lines
1.5 KiB
Plaintext
* ARM Versatile FPGA interrupt controller
|
|
|
|
One or more FPGA IRQ controllers can be synthesized in an ARM reference board
|
|
such as the Integrator or Versatile family. The output of these different
|
|
controllers are OR:ed together and fed to the CPU tile's IRQ input. Each
|
|
instance can handle up to 32 interrupts.
|
|
|
|
Required properties:
|
|
- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
|
|
- interrupt-controller: Identifies the node as an interrupt controller
|
|
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
|
|
as the FPGA IRQ controller has no configuration options for interrupt
|
|
sources. The cell is a u32 and defines the interrupt number.
|
|
- reg: The register bank for the FPGA interrupt controller.
|
|
- clear-mask: a u32 number representing the mask written to clear all IRQs
|
|
on the controller at boot for example.
|
|
- valid-mask: a u32 number representing a bit mask determining which of
|
|
the interrupts are valid. Unconnected/unused lines are set to 0, and
|
|
the system till not make it possible for devices to request these
|
|
interrupts.
|
|
|
|
Example:
|
|
|
|
pic: pic@14000000 {
|
|
compatible = "arm,versatile-fpga-irq";
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
reg = <0x14000000 0x100>;
|
|
clear-mask = <0xffffffff>;
|
|
valid-mask = <0x003fffff>;
|
|
};
|
|
|
|
Optional properties:
|
|
- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
|
|
output is simply connected to the input of another IRQ controller,
|
|
then the parent IRQ shall be specified in this property.
|